On-chip differential multi-layer inductor

Details On-chip differential multi-layer inductor On-chip differential multi-layer inductor

2006-08-15

2006-08-15

Nguyen, Tuyen T (Department: 2832)

Inductor devices

Coil or coil turn supports or spacers

Printed circuit-type coil

Reexamination Certificate

active

07091814

ABSTRACT:
An on-chip differential multi-layer inductor includes a 1stpartial winding on a 1stlayer, a 2ndpartial winding on the 1stlayer, a 3rdpartial winding on a 2ndlayer, a 4thpartial winding on the 2ndlayer, and an interconnecting structure. The 1stand 2ndpartial windings on the 1stlayer are operably coupled to receive a differential input signal. The 3rdand 4thpartial windings on the 2ndlayer are each operably coupled to a center tap. The interconnecting structure couples the 1st, 2nd, 3rdand 4thpartial windings such that the 1stand 3rdpartial windings form a winding that is symmetrical about the center tap with a winding formed by the 2ndand 4thpartial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined. Having determined the electrical parameters of the multi layer established, the geometric shapes of the windings, number of windings, number of layers to support the inductor, and the interconnecting structure may be determined.

REFERENCES:
patent: 5477204 (1995-12-01), Li
patent: 6396362 (2002-05-01), Mourant et al.
patent: 6476704 (2002-11-01), Goff
patent: 6707367 (2004-03-01), Castaneda et al.
patent: 6759937 (2004-07-01), Kyriazidou
patent: 6801114 (2004-10-01), Yang et al.
patent: 2001/0017582 (2001-08-01), Sakata

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