On-chip design-for-testing structure for CMOS APS (active...

Details On-chip design-for-testing structure for CMOS APS (active... On-chip design-for-testing structure for CMOS APS (active...

2001-06-29

2004-09-28

Pyo, Kevin (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C348S308000

Reexamination Certificate

active

06797933

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic circuits and semiconductor devices that will receive light and convert the light to an electronic signal representing the amplitude of the light commonly referred to as photo-sensors or pixel sensors. More particularly this invention relates to methods and apparatus for testing light sensing devices, circuits, and blocks. This invention further identifies the use of such DFT methods and apparatus for testing of functionality and manufacturing process values to assure the operation of photosensors or pixel sensors in providing reliable and accurate electronic shuttering of captured light information as an array of pixels. This invention especially relates to methods and apparatus for testing of circuits and blocks known as active pixel sensors (APS).
2. Description of Related Art
Imaging circuits typically include a two dimensional array of photo-sensors. Each photo-sensor comprises one picture element (pixel) of the image. Light energy emitted or reflected from an object impinges upon the array of photo-sensors The light energy is converted by the photo-sensors to an electrical signal. Imaging circuitry scans the individual photo-sensors to readout the electrical signals. The electrical signals of the image is processed by external circuitry for subsequent display.
Modern metal oxide semiconductor (MOS) design and processing techniques have been developed that provide for the capture of light as charge and the transporting of that charge within APS and other structures so as to be accomplished with almost perfect efficiency and accuracy.
U.S. Pat. No. 5,841,126 (Fossum, et. al.) describes a CMOS active pixel sensor (APS) type imaging system on a chip. The imaging system consists of an APS and a controller on a single substrate. The controller provides specialized support electronics that are integrate onto the same substrate as the APS array. The controller includes integration, timing, control electronics, signal chain electronics, A/D Conversion, and other important control systems.
U.S. Pat. No. 5,900,623 (Tsang, et. al.) describes an active pixel sensor implemented with CMOS technology that employs an array of photocells. Each cell includes a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode. Each photocell includes a switching network that couples the photocurrent to the storage node only during the integration period while ensuring that a relatively constant voltage is maintained across the photodiode during integration and non-integration periods.
While the prior art patents describe the system, circuitry, functioning, and timing of pixel circuits and APS. None of the patents include any aspects of testing apparatus and methods for testing functionality, evaluating performance or determining capacitance of an APS.
FIG. 1
shows a typical CMOS Active Pixel Sensor (APS) of the prior art, using a photo-diode as a photo-conversion device for example. The drain terminals of the transistors M
1
and M
2
are connected to the power supply voltage distribution line, V
DD
. The source of the transistor M
2
is connected to the anode of the photo-diode D
F
. The cathode of the photo-diode is connected to the ground reference point. The capacitance C
FD
is the inherent capacitance of the photo-diode D
F
.
The gate of the transistor M
2
is connected to a reset terminal to receive the reset signal V
rst
. The sensor readout node FD, that is the anode of the photo-diode D
F
, is first reset to a high voltage level (V
DD
) by changing the reset signal V
rst
from a low voltage level (0) to a high voltage level (V
DD
) to charge the capacitance C
FD
. At the completion of charging the capacitance C
FD
, the reset signal V
rst
is changed from the high voltage level (V
DD
) to the low voltage level. Since light is shown on the photo-diode D
F
, photo-generated electrons are collected at node FD and the voltage at the node FD decreases in the process. At the end of the exposure duration the voltage at node FD is measured, thus completing one photo-sensing cycle. The photo-sensing cycle is completed by deactivating the transistor M
3
by changing the row select signal from the high voltage level (V
DD
) to the low voltage level (0).
The gate of the transistor M
1
is connected to the node FD and the source of the transistor M
1
is connected to the drain of the transistor M
3
. The transistor M
1
acts as a source follower such that the voltage present at the source of the transistor M
1
“follows” directly the voltage present at the gate of the transistor M
1
and is one transistor threshold voltage V
T
below the voltage present at the gate of the transistor M
1
.
The gate of the transistor M
3
is connected to the row select line to receive the row select signal V
row
. The source of the transistor M
3
is connected to the column bus ColBus. The column bus interconnects all the APS's present on a column of an array of APS's. When the row select signal changes from a low voltage level (0V) to a high level (V
DD
), the transistor M
3
turns-on and the voltage present at the source of the transistor M
1
is transferred to the output of the APS to couple the voltage that is proportional to the intensity of the light L. The output signal V
out
—
pixel
of the APS is coupled to the column bus ColBus for further conditioning and readout.
An APS signal conditioning and readout circuit as shown in FIG.
2
and described in Fossum, et. al. is connected to the column bus ColBus of each column of APS's of an array of APS's. The APS signal and readout circuit employs correlated double sampling (CDS) to determine the level of the light L impinged upon the photodiode D
f
. Correlated double sampling (CDS) is achieved by sampling both a reset reference level and a signal level. The difference between the signal level and the reset reference level represents the net signal induced by level of the light L illuminating the photodiode D
F
. The resulting voltage of the node FD is read out through the transistors M
1
and M
3
of the APS pixel circuit of
FIG. 1
onto the column bus ColBus. The voltage V
out
—
pixel
on the column bus ColBus is sampled onto a first holding capacitor C
1
by an activation pulse SHR to the gate of the transistor M
6
. This initial charge is used as the baseline. After raising the reset signal V
rst
, the signal charges within the APS pixel circuit due to the impinging of photoelectrons and the capacitance C
FD
. The resulting voltage V
out
—
pixel
is also transferred onto the column bus ColBus and sampled onto a second holding capacitor C
2
by an activation pulse SHS to the gate of the transistor M
5
. The difference between the voltages on the first capacitor C
1
and the second capacitor C
2
is therefore indicative of the number of photoelectrons of the light L that were allowed to enter the photodiode D
f
.
A key element in the calculation of the conversion gain in a CMOS APS imager pixel is the measurement of the capacitance C
FD
at the pixel readout node, FD.
In the prior art, a conventional APS test scheme used to measure the capacitance is shown in FIG.
3
. To summarize how such an APS test approach is used, a photo-diode pixel of
FIG. 1
is used as an example.
The structure of
FIG. 1
is modified such that the drain connections of the transistors M
1
and M
2
are separately connected. The drain of M
1
is now connected to the supply line, V
DD
1
, while the drain of M
2
is connected to another supply line, V
DD
2
.
The voltage source VS
1
driving the supply line V
DD
1
is set to a voltage level of the power supply voltage source V
DD
. A second voltage source connected to the V
DD
2
line is also set to the same value, the power supply voltage source V
DD
. Bright light is shown on the pixel so that it is saturated. The reset signal V
rst
is pulsed periodically and the resulting average current from the voltage source

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