On-chip decoupling capacitor system with parallel fuse

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit

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Details

327380, 3652257, H01H 8500

Patent

active

060844647

ABSTRACT:
An-on-chip decoupling capacitor system for an integrated circuit comprises parallel capacitive and fusible paths between power and ground. The capacitive path includes a field-effect-transistor based capacitor and another "capacitive-path" transistor in series with the capacitor. The fusible path includes an electromigratable fuse and a "fusible-path" transistor in series with the fuse. The capacitive-path transistor, which is controlled by the voltage at a "fusible-path" node between the fuse and the fusible-path transistor, is on during normal operation. The fusible-path transistor, which is controlled by the voltage at a "capacitive-path" node between the capacitor and the capacitive-path transistor, is off during normal operation. During normal operation, the capacitor provides local voltage regulation by sinking charge during voltage surges and supply charge during voltage drops. In the event of the capacitor is shorted due to a dielectric breakdown, the series capacitive-path transistor serves as a current limiter. A rise in voltage at the capacitive-path node turns on the fusible-path transistor--urging current through the fuse. Electromigration causes the fuse to break. This drops the voltage at the fusible-path node so that the capacitive-path transistor is turned off. At this point, there is no current through either path and the decoupling capacitor system is functionally removed from the incorporating integrated circuit.

REFERENCES:
patent: 5506457 (1996-04-01), Krauter et al.
patent: 5789964 (1998-08-01), Voldman
patent: 5828259 (1998-08-01), Cases et al.
Nam Pham, Moises Cases, and Bhupindra Singh "On-Chip Decoupling Capacitor Design and Modeling Methodology", Proceedings of DesignCon, 1999, pp. 57-70.

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