On chip decap trench capacitor (DTC) for ultra high...

Details On chip decap trench capacitor (DTC) for ultra high... On chip decap trench capacitor (DTC) for ultra high...

2003-04-03

2004-11-30

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S301000

Reexamination Certificate

active

06825545

ABSTRACT:

BACKGROUND OF INVENTION
The present invention generally relates to integrated circuit (IC) structures in complementary metal oxide semiconductor (CMOS) circuits and, more particularly, to a new method for integrating an embedded high capacitance, low leakage decoupling capacitor on silicon on insulator (SOI) or bulk wafers for very high performance CMOS microprocessors.
The goal for semiconductor designers is to design highly reliable, super high performance CMOS microprocessors with ever increasing functionality requirements, while consuming the lowest possible power. This becomes more important for low power battery operated devices where battery operating lifetime is crucial.
In this mode of operation, circuit designers face a number of challenges to insure high signal integrity within the chip and the semiconductor package. Simultaneous switching through the input and output (I/O) pins give to current “noise” spike &dgr;I within a specified time, severely degrading the signal integrity. The signal integrity is jeopardized mainly by the “noise” on the power and ground planes due to the capacitance coupling between power and signal lines. These noises become more severe as the clock frequency or the I/Q pin count is increased.
To insure the system reliability against such deleterious effects, decoupling capacitors, known as Decap, are added to the power and ground planes to provide an AC ground for the noise and provide a stable DC voltage. The value of the Decap is usually modeled by:
Decoupling Cap (Decap)=Current spike &dgr;
I
×Time/(&dgr;
V
Voltage Noise)
Currently, the methodology for embedding a Decap on a microprocessor is to use available structures in the semiconductor process flow; i.e., N-type field effect transistor (NFET), P-type field effect transistor (PFET), or capacitors, all of which strongly depend on the thickness of the gate oxide (Tox) used to meet the necessary capacitance predicted in the above equation. As oxide thickness is scaled down, in order to increase the capacitance value in a preset silicon active area, the gate current leakage will increase accordingly. It has been determined experimentally that the gate leakage current increases by a factor of 2.5-3 times for every 1 Angström (1 Å) of gate oxide scaling.
In order to increase the gate capacitance and reduce power dissipation and at the risk of increased process complexity and cost, it is possible to build a process with multiple gate oxide offering:
the “thin gate oxide” for high performance NFET and PFET devices;
the other “thick gate oxide” for the Decap capacitance with limited leakage value to reduce the power dissipation, but reduced capacitance; and
another possible method is to introduce a third “intermediate” gate oxide which balances the increased gate capacitance, but at the risk of increased gate leakage.
State of the art microprocessor Decap requires as much as a micro Farad (1 &mgr;F) designed in a half centimeter square area (0.5 cm
2
). A significant amount on a required silicon real estate area in light of the reduced number of chips which can be placed on a wafer and the reduced profit associated with this.
Table 1 describes an example of an available microprocessor surface area which can be used to obtain a Decap requirement of 1 &mgr;F, using various thin and thick oxide values. As an example, DG represents the “thick gate oxide” of 22 Å, the “thin gate oxide” of 10 Å or a combined area of “thin” and “thick” and “intermediate” gate oxide of 15 Å.
[t1]
TABLE 1
1 &mgr;F Decap Area Requirements
Decap Area (cm
2
)
Necessary for 1 &mgr;F
DG +
Decap
DG (22 Å)
DG + Thin (10 Å)
Intermediate (15 Å)
Case 1
0.54 cm
2
Case 2
0.34 + 0.21 cm
2
Case 3
0.34 + 0.21 cm
2
FIG. 1
shows the calculated Decap value in micro Farads (&mgr;F) as a function of gate oxide thickness in nanometers for an available area of 0.54 cm
2
on a typical high performance microprocessor design. Note that for a robust signal integrity design, a Decap capacitance of 1 &mgr;F is required, where only 0.6 to 0.8 &mgr;F can be provided using the current planar gate oxide decap method and the limited set silicon area.
FIG. 2A
shows the current standard method of forming a planar Decap on SOI, starting with a thin gate oxide on silicon wafer which forms the bottom plate of the capacitor. Although the object of the invention is not the Silicon On Insulator (SOI) formation itself, it is described here for clarity of understanding the preferred embodiment of the invention. One method of forming such an SOI substrate wafer is through the implantation of oxygen specie at high energy as to embed the oxygen deep in the silicon substrate
1
and leave a layer of silicon
3
free from oxygen on top of the oxygen level. This is followed by an annealing step at high temperature, which results in the formation of a buried silicon dioxide (BOX) layer
2
, below a shallow silicon layer, (layer
3
) on top of the BOX layer
2
on the silicon substrate
1
.
The silicon layer
3
is divided into regions by shallow trench insulation (STI)
4
and, by process of patterning with photoresist and doping well known in the art, the respective regions are made to be n-type or p-type regions, as shown. The structure is then wet cleaned, and a thick gate oxide
5
is formed. Then a photoresist is spun on, patterned and developed to protect the thick gate oxide. The exposed area is then wet etched to remove the unprotected thick gate oxide. Next, the photoresist is stripped and a thin gate oxide
6
is grown.
FIG. 2B
shows a standard method for gate interconnect polysilicon deposition to form the top plate of the capacitor. More specifically, a low pressure chemical vapor deposition (LPCVD) of polysilicon
7
covers the entire structure to a thickness of 150 nm. Then, by plasma enhanced chemical vapor deposition (PECVD), a 50 nm layer of gate capacitor oxide
8
is deposited. An anti-reflective coating (ARC)
9
to a thickness of 90 nm is deposited, followed by a photoresist layer
10
to a thickness of 240 nm. The photoresist layer
10
is patterned, exposed and developed to form the mask in the form of 70 nm wide resist lines.
FIG. 2C
shows a planar Decap polysilicon lithographic pattern. Although only single fingers of polysilicon are shown for the sake of clarity, in practice the Decap must be designed with multiple fingers of polysilicon lines for defect reasons. After etching back to the thick and thin gate oxides
5
and
6
, the photoresist
10
and the anti-reflective coating
9
are stripped, leaving the polysilicon lines
11
.
The left sides of
FIGS. 3A and 3B
show, respectively, a top view and a side view in schematic representation of the planar Decap structure formed by the process described with respect of
FIGS. 2A
,
2
B and
2
C. It will be immediately apparent from
FIG. 3A
the relatively large active area required by the planar Decap structure.
SUMMARY OF INVENTION
It is therefore an object of the present invention to provide a new structure and process to form a new Decap Trench Capacitor (DTC) which provides increased capacitance within in a smaller active silicon area than prior planar Decap capacitors.
It is another object of the invention to provide a new semiconductor method of integrating Decap trench capacitors on SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the active silicon area used.
According to one aspect of the invention, there is provided a new semiconductor Decap Trench Capacitor (DTC) integrated on a SOI for the purpose of accomplishing a robust circuit design with low noise while reducing the silicon area used. The DTC for SOI devices comprises a buried oxide layer on a silicon substrate with a silicon layer over the buried oxide layer. Shallow trench insulation extends to the buried oxide layer in the silicon layer. A first trench is formed in the shallow trench insulation and extends through the buried oxide layer into the silicon substrate. The first trench has formed

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