On-chip capacitor

Details On-chip capacitor On-chip capacitor

2000-01-11

2003-04-01

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S528000, C257S532000

Reexamination Certificate

active

06541840

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an on-chip capacitor which functions as a capacitance device formed in a semiconductor integrated circuit.
PRIOR ART
FIG. 6
shows the structure of an MOS capacitance of a conventional semiconductor integrated circuit. FIG.
6
(
a
) is a plan view, (
b
) is a cross sectional view along the line A-B and (
c
) is an equivalent circuit. In the figures, reference numeral
61
denotes a P-type silicon substrate,
62
is an N-well region formed on the P-type silicon substrate
61
,
63
is an N+ dispersion region forming a source and drain electrode,
64
is a gate electrode,
65
is an oxide film formed on the N-well region
62
and the P-type silicon substrate
61
.
FIG. 7
shows the structure of a poly-silicon capacitance of a conventional semiconductor integrated circuit. FIG.
7
(
a
) is a plan view, (
b
) is a cross sectional view along the line A-B and (
c
) is an equivalent circuit. In the figures, reference numeral
71
denotes a P-type silicon substrate,
72
is an oxide film formed on the P-type silicon substrate
71
,
73
is a lower poly-silicon gate, and
74
is an upper poly-silicon gate electrode.
FIG. 8
shows the structure of a CMOS device of a conventional semiconductor integrated circuit. FIG.
8
(
a
) is a plan view, (
b
) is a cross sectional view along the line A-B and (
c
) is an equivalent circuit. In the figures, reference numeral
81
denotes a P-type silicon substrate,
82
is an N-well region formed on the P-type silicon substrate
81
,
83
is a P-well region formed on the P-type silicon substrate
81
and connected to a grounding power source VSS (GND),
84
is a P+ dispersion region,
85
is an N+ dispersion region,
86
is an NMOS poly-silicon gate electrode,
87
is PMOS poly-silicon gate electrode and
88
is an oxide film.
The operation of the invention will be described below.
A conventional semiconductor integrated circuit uses a MOS capacitance having the structure shown in
FIG. 6 and a
poly-silicon capacitance having the structure shown in
FIG. 7
as a capacitance device. When such capacitance devices are connected between a power source VCC and a grounding power source VSS (GND), the devices act as a decoupling capacitor with respect to the power source and GND noise.
A CMOS device which comprises the conventional semiconductor integrated circuit shown in
FIG. 8
is provided with a PMOS in an N-well region
82
connected to the power source (VCC) and a NMOS in a P-well region
83
connected to the grounding power source (GND). A PN junction is formed between the N-well region
82
and the P-well region
83
and a capacitance component is formed by separating the N-well region
82
and the P-well region
83
electrically. A capacitance is formed between the power source (VCC) and the grounding power source (GND). Only the coupling surface between the N-well region
82
and the P-well region
83
contributes to the capacitance.
Since a decoupling capacitor in a conventional semiconductor integrated circuit is formed as above, it is possible for the capacitor to stabilize a power source voltage and to function as a decoupling capacitor with respect to noise from the power source and the grounding power source (GND). However in order to form these decoupling capacitors in the semiconductor integrated circuit, it is necessary to form a MOS capacitance or a silicon capacitance on the silicon substrate and to connect such a terminal to the power source (VCC) and the grounding power source (GND). In order to dispose the device, it is necessary to provide the required region and required wiring. Thus the problem has arisen that the effective disposable space to dispose the device in the semiconductor integrated circuit is reduced. Furthermore in the conventional CMOS device as shown in
FIG. 8
the depth of the N-well region
82
and the P-well region
83
is only of the order of a few &mgr;m. Thus the problem has arisen that it is not possible to achieve a decoupling capacitance of a required capacitance in the semiconductor integrated circuit chip.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the above problems and has the object of providing an on-chip capacitor capable of forming a capacitor device having a capacitance required between a power source voltage VCC and a grounding power source VSS (GND) and which does not require a device region or a wiring region on the semiconductor integrated circuit chip.
The on-chip capacitor of the present invention is provided with a P-type silicon substrate, a bottom N-well region formed on said P-type silicon substrate, mutually adjacent first P-well and first N-well regions formed on said bottom N-well region, a first electrode formed on said first N-well region, and a second electrode formed on said first P-well region. A coupling surface is formed with said first N-well region and said first P-well region and a capacitance between a power source voltage and a grounding voltage is formed between said first P-well region and said bottom N-well region.
The on-chip capacitor of the present invention forms a fixed number of second N-well regions without transistors or dispersion regions in said first P-well region.
The on-chip capacitor of the present invention is provided with a coupling region in said bottom well region instead of said second electrode so that said first P-well region and said P-type silicon substrate are connected.
The on-chip capacitor of the present invention is provided with an N-type silicon substrate, a bottom P-well region formed on said N-type silicon substrate, mutually adjacent first N-well and first P-well regions formed on said bottom P-well region, a first electrode formed on said first P-well region, and a second electrode formed on said first N-well region, a coupling surface is formed with said first N-well region and said first P-well region and a capacitance between a power source voltage and a grounding voltage capacitance is formed between said first P-well region and said bottom N-well region.
The on-chip capacitor of the present invention forms a fixed number of second P-well regions without transistors or dispersion regions in said first N-well region.
The on-chip capacitor of the present invention is provided with a coupling region in said bottom P-well region instead of said first electrode so that said first N-well region and said N-type silicon substrate are connected.


REFERENCES:
patent: 5786617 (1998-07-01), Merrill et al.

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