On chip buffering for optimizing performance of a bubble memory

Details On chip buffering for optimizing performance of a bubble memory On chip buffering for optimizing performance of a bubble memory

1977-11-21

1979-05-01

Moffitt, James W.

Static information storage and retrieval

Magnetic bubbles

Plural interacting paths

365 12, 365 17, G11C 1908

Patent

active

041527771

ABSTRACT:
In a bubble memory system having storage loop architecture, means for buffering both read and write requests in order to improve performance including, in the embodiment disclosed, two sets of short or buffer loops, one for the write section and one for the read section, which are virtually asynchronous with respect to each other and to the main memory storage loops and in which data may be temporarily stored prior to transfer into the main storage loops or prior to transfer into an output track.

REFERENCES:
patent: 4056812 (1977-11-01), Bobeck et al.

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