On-chip bit reordering structure

Details On-chip bit reordering structure On-chip bit reordering structure

1986-09-15

1989-07-04

Shaw, Gareth D.

Boots, shoes, and leggings

371 38, G06F 722, G06F 1110, H03M 1300

Patent

active

048456640

ABSTRACT:
An apparatus and method whereby a static column mode DRAM can access a unique data bit located anywhere within the array chip and sustain a continuous transfer of requested bits in a contiguous group of bits (i.e. block). Steering of the data in a prescribed order is accomplished via a special steering and gating network. A control line, toggle, is used on both rising and falling edges to produce this gapless transfer.

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IBM TDB vol. 24, No. 1B, Jun. 1981; vol. 24, No. 4, Sep. 1981.
IBM Journal vol. 28, No. 2, Mar. 1984.

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