On chip bi-stable power-spike detection circuit

Details On chip bi-stable power-spike detection circuit On chip bi-stable power-spike detection circuit

1992-06-22

1994-11-01

Wieder, Kenneth A.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

3241581, G01R 3102

Patent

active

053610334

ABSTRACT:
A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

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patent: 4685086 (1987-08-01), Tran
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patent: 4794332 (1988-12-01), Schweitzer, Jr.
patent: 5070426 (1991-12-01), Iwasa et al.
patent: 5084873 (1992-01-01), Houston
patent: 5157335 (1992-10-01), Houston

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