On board self-calibration of analog-to-digital and digital-to-an

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340347AD, 340347DA, 364571, H03K 1302

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043994261

ABSTRACT:
A method and apparatus is disclosed which corrects for errors produced in data acquisition systems. Disclosed is a method and circuit for correcting errors, such as mismatch between binary weighted capacitors and offset, in a charge redistribution, weighted capacitor array analog-to-digital converter. A self-calibrating, self-correcting circuit is comprised of a second binary array of capacitors which adds to the regular charge redistribution capacitor array an error correcting signal to compensate for the mismatch. This error correcting signal is then stored and the other error correcting signals for other capacitors in the regular capacitor array are determined and subsequently stored for later correction of other capacitance mismatch.

REFERENCES:
patent: 4129863 (1978-12-01), Gray
patent: 4222107 (1980-09-01), Mrozowski
patent: 4272760 (1981-06-01), Prazak
Croisier, "IBM Technical Disclosure Bulletin" vol. 18, No. 8, Jan. 1976, pp. 2538-2539.
Schulz "IBM Technical Disclosure Bulletin" vol. 16, No. 1 Jun. 1973, pp. 137-138.

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