Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1996-05-23
2001-02-13
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S383000, C257S076000, C257S079000
Reexamination Certificate
active
06188137
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an ohmic electrode structure provided in a compound semiconductor device, a semiconductor device including such an ohmic electrode structure; and a method for producing such a semiconductor device.
2. Description of the Related Art
In a conventionally known method for providing ohmic contact with an n-GaAs layer in a compound semiconductor device, an In
x
Ga
1−x
As layer (0<x≦1) is epitaxially grown on an n-GaAs layer, and then a metal or alloy layer is formed thereon.
FIGS. 9 and 10
each show a conventional ohmic electrode structure.
In the structure shown in
FIG. 9
, an In
x
Ga
1−x
As layer
2
is provided on an n-GaAs substrate
1
, and a Ti layer
41
, a Pt layer
42
and a Au layer
43
are provided on the In
x
Ga
1−x
As layer
2
in this order. The Ti layer
41
, the Pt layer
42
and the Au layer
43
form an electrode.
In such a structure, since the three metal layers
41
through
43
forming the electrode easily react with the In
x
Ga
1−x
As layer
2
which is lattice-mismatched, the heating temperature cannot be very high after the electrode is formed. For example, when the structure is heated at 390° C. for 1 minute, the contact resistance &rgr;c increases by about three orders, from 1×10
−8
&OHgr;cm
2
to 1×10
−5
&OHgr;cm
2
.
In the structure shown in
FIG. 10
, which is disclosed in Japanese Laid-Open Patent Publication No. 1-194468, a barrier layer
5
formed of tungsten silicide (WSi) is interposed between the In
x
Ga
1−x
As layer
2
and the Ti layer
41
.
In such a structure, the contact resistance is stable with no significant increase even if the structure is heated at 400° C. or more due to the presence of the barrier layer
5
. However, in the case when the barrier layer
5
is formed by sputtering, it is difficult to obtain a desirable composition for the barrier layer
5
because the sputtering efficiency of tungsten is different from that of silicon. Further, the purity of WSi, which is a sintered body, cannot be very high. Moreover, WSi is generally present in a columnar polycrystalline structure, and thus is difficult to process, which complicates the formation of the ohmic electrode structure.
In a conventional semiconductor device such as a heterojunction bipolar transistor (HBT) including semiconductor layers respectively having p-type and n-type conductivities on one substrate, different electrodes need to be formed respectively for the semiconductor layers. This is because materials which can be used for different electrodes to be in ohmic contact with the p-type and n-type semiconductor layers are different from each other. Thus, the fabrication process of the semiconductor device is complicated, and the electrodes easily become non-uniform in thickness and characteristics.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, an ohmic electrode structure includes an n-In
x
Ga
1−x
As layer where 0<x≦1; a Pt layer provided on the n-In
x
Ga
1−x
As layer; and at least one metal layer provided on the Pt layer.
According to another aspect of the present invention, an ohmic electrode structure includes an n-In
x
Ga
1−x
As layer where 0<x≦1; a Pd layer provided on the n-In
x
Ga
1−x
As layer; and at least one metal layer provided on the Pd layer.
According to still another aspect of the present invention, a semiconductor device includes a substrate; a first semiconductor layer having a p-type conductivity provided on the substrate; a second semiconductor layer having an n-type conductivity provided on the substrate; an ohmic contact layer provided on the first semiconductor layer; a barrier layer provided on the second semiconductor layer; a first electrode provided on the ohmic contact layer; and a second electrode provided on the barrier layer. The ohmic contact layer and the barrier layer are each formed of a material selected from the group consisting of Pt and Pd.
According to still another aspect of the present invention, a method for producing a semiconductor device includes the steps of forming a multi-layer structure including a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type on a semiconductor substrate; forming a layer of a metal selected from the group consisting of Pt and Pd so as to cover the first semiconductor region and the second semiconductor region; forming at least one metal layer on the layer of the metal selected from the group consisting of Pt and Pd; and patterning the at least one metal layer and the layer of the metal selected from the group consisting of Pt and Pd to form at least on ohmic electrode on each of the first semiconductor region and the second semiconductor region.
Thus, the invention described herein makes possible the advantages of (1) providing an ohmic electrode structure which remains stable in contact resistance after heating at a high temperature and can be produced relatively easily, and (2) providing a semiconductor device including an ohmic electrode structure which can be in ohmic contact with semiconductor layers of both p-type and n-type conductivities and a method for producing the same.
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IEEE Electron Device Letters, vol. EDL-8, No. 11, Nov. 1987, pp. 534-536.
Electronics Letters 21stJan. 1988, vol. 24, No. 2, pp. 93-94.
Koichi Nagata et al, “Self-Aligned A1GaAs/GaAs HBT with Low Emitter Resistance Utilizing InGaAs Cap Layer”, IEEE Transactions On Electron Devices, vol. ED-35, No. 1, pp. 2-7, Jan. 1988).
T. Iwai et al, “1.5V Low-Voltage Microwave Power Performance of InA1As/InGaAs Double Heterojunction Bipolar Transistors”, Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials, Osaka, 1995, pp. 386-388.
Sato Hiroya
Yagura Motoji
Clark Jhihan B.
Saadat Mahshid
Sharp Kabushiki Kaisha
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