Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-03-22
2001-11-06
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S013000, C257S748000, C257S763000, C257S750000, C257S766000, C257S775000
Reexamination Certificate
active
06313534
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P10-077201 filed Mar. 25, 1998 which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an ohmic electrode, method for making same and multi-layered structure for making same, and particularly relates to an ohmic electrode for a III-V compound semiconductor base body.
2. Description of the Related Art
To grade up the performance and improve the reliability of a device, such as FET, using compound semiconductors, reduction of contact resistance and improvement of thermal stability of its ohmic electrode are important issues. Heretofore, however, as to ohmic electrodes for compound semiconductors, especially such as GaAs semiconductors and other III-V compound semiconductors, there has been proposed none that satisfies the above-mentioned requirements.
Ohmic electrodes currently brought into practical use or under proposal can be roughly classified into three groups. In first group ohmic electrodes, used as their ohmic metals are materials containing an element behaving as a donor impurity relative to GaAs semiconductors. Then, the ohmic electrode are made by annealing the material to have the element diffuse into a semiconductor to form an n-type region with a high impurity concentration along the boundary between an electrode metal and the semiconductor and make an ohmic contact by tunneling effect, for example. In second group ohmic electrodes, used as their ohmic electrodes are materials containing an element which makes an intermediate layer with a low energy barrier. Then, the ohmic electrodes are made by annealing the materials to form such an intermediate layer with a low energy barrier between the electrode metal and the semiconductor to lower the energy barrier in the portion where carriers flow, thereby to make an ohmic contact. In third group ohmic electrodes, used as their ohmic metals are materials containing an element which interacts with a GaAs semiconductor, when annealed, and forms a semiconductor re-grown layer, and another element which behaves as a donor impurity relative to GaAs. Then, the ohmic electrodes are made by annealing the materials to form a re-grown layer and change the re-grown layer into an n-type layer with a high impurity concentration, thereby to make an ohmic contact by tunneling effect, for example.
A representative example of first group ohmic electrodes is shown in
FIGS. 1A and 1B
. In this example, a AuGe/Ni thin film
102
is made as an ohmic metal on an n
+
-type GaAs substrate
101
as shown in
FIG. 1A
, and it is annealed at 400° C. through 500° C. to form the ohmic electrode as shown in FIG.
1
B. In
FIG. 1B
, reference numeral
103
denotes an n
++
-type GaAs layer, and
104
denotes a layer containing a mixture of NiAs and &bgr;-AuGa.
However, the ohmic electrode shown in
FIG. 1B
is unsatisfactory in thermal stability. More specifically, since a plenty of Au contained in the AuGe/Ni film
102
as the ohmic metal (normally used AuGe contains 88% of Au) forms &bgr;-AuGa in the layer
104
by interaction with the n
+
-type GaAs substrate
101
when annealed at a temperature of 400° C. or higher, the contact resistance of the ohmic electrode increases significantly. This induces deterioration of the device characteristics occurs upon a high-temperature process such as chemical vapor deposition (CVD) conducted after the ohmic electrode is made. Moreover, generation of &bgr;-AuGa by interaction between the n
+
-type GaAs substrate
101
and Au in the AuGe/Ni thin film
102
makes a rough surface on the ohmic electrode, and this invites problems upon later micro processing.
The ohmic electrode shown in
FIG. 1B
involves another problem that it cannot cope with the requirements of reducing the thickness of the n
++
-type GaAs layer
103
or micro-sizing FET or other devices. More specifically, the n
++
-type GaAs layer
103
, which is made by diffusion upon annealing, is determined in depth and lateral extension (extension parallel to the substrate) exclusively by the annealing temperature and time. Therefore, its depth and lateral direction cannot be controlled. As a result, it is difficult to reduce the thickness of the n
++
-type GaAs layer
103
and the distance between ohmic electrodes.
Second group ohmic electrodes and third group ohmic electrodes were proposed to overcome the problems involved in the above-discussed first group ohmic electrode due to the use of AuGe/Ni thin film
102
, namely, thermal instability of the ohmic electrode and roughness on the electrode surface.
A representative example of second group ohmic electrodes is shown in
FIGS. 2A and 2B
. In this example, a NiIn thin film
202
and a W thin film
203
as ohmic metals are stacked sequentially on an n
+
-type GaAs substrate
101
as shown in
FIG. 2A
, and they are annealed at a high temperature around 900° C. for about one second to form the ohmic electrode as shown in FIG.
2
B. In
FIG. 2B
, reference numeral
204
denotes an InGaAs (simplified expression of In
x
Ga
1−x
As throughout this application) layer, and
205
denotes Ni
3
In thin film. In this case, the InGaAs layer
204
is made as an intermediate layer with a low energy barrier as a result of interaction between the n
+
-type GaAs substrate
201
and In contained in the NiIn thin film
202
in the annealing process, and decreases the effective height of the energy barrier to make the ohmic contact. Since the ohmic electrode shown in
FIG. 2B
does not contain any refractory compound, such as &bgr;-AuGa contained in the first group ohmic electrode shown in
FIG. 1B
, it is reported that the contact resistance of the ohmic electrode is stable against annealing at 400° C. for 100 hours, approximately.
The ohmic electrode shown in
FIG. 2B
, however, needs high-temperature annealing around 900° C. to make the ohmic contact. Therefore, it cannot be used in devices, such as JFET (junction gate FET) and HEMT (high electron mobility transistor), which use gates and channels formed at a temperature lower than 900° C. Therefore, the ohmic electrode shown here has the problems that the process window is small and its applicability is limited to a few sorts of devices.
A representative example of third group ohmic electrodes is shown in
FIGS. 3A and 3B
. In this example, a Pd thin film
302
and a Ge thin film
303
are sequentially stacked as ohmic metals on an n
+
-type GaAs substrate as shown in
FIG. 3A
, and they are annealed at 325° C. through 375° C. for 30 minutes, approximately, to form the ohmic electrode as shown in FIG.
3
B. In
FIG. 3B
, reference numeral
304
denotes an n
++
-type GaAs layer and
305
denotes a PdGe thin film. In this case, GaAs from the n
+
-type GaAs substrate
301
makes a re-grown layer, and Ge from the Ge thin film
303
diffuses in the re-grown layer to form the n
++
-type GaAs layer
304
and thereby makes the ohmic contact.
In the ohmic electrode shown in
FIG. 3B
, the thickness of the re-grown n
++
-type GaAs layer
304
can be controlled by changing the thickness of the Pd thin film
302
and/or the Ge thin film
303
. Therefore, it is possible to reduce the thickness of the n
++
-type GaAs layer
304
and the distance between ohmic electrodes. However, the ohmic electrode shown here has a serious problem about its thermal stability.
Under the circumstances, the Inventor proposed a new method for making ohmic electrodes intended to overcome the problems contained in ohmic electrodes in first, second and third groups discussed above Japanese Patent Laid-Open Publication No. Hei 6-267887).
FIGS. 4A and 4B
illustrate this method. As shown in
FIG. 4A
, this method first makes a predetermined pattern of a Ni thin film
402
, IN thin film
403
and Ge thin film
404
on an n
+
-type GaAs substrate
401
as shown in FIG.
4
A. In this ca
Murakami Masanori
Nakamura Mitsuhiro
Ogura Mitsumasa
Smith Matthew
Sonnenschein Nath & Rosenthal
Sony Corporation
Yevsikov V.
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