Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Heterojunction formed between semiconductor materials which...
Reexamination Certificate
1999-09-16
2001-08-28
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Heterojunction formed between semiconductor materials which...
C257S194000, C257S195000, C257S192000
Reexamination Certificate
active
06281528
ABSTRACT:
RELATED APPLICATION DATA
The present application claims priority to Japanese Application No. P10-264862 filed Sep. 18, 1998 which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a compound semiconductor device and a method for manufacturing the same and, more in particular, it relates to an electrode structure of a compound semiconductor, a semiconductor device such as an FET or HEMT, as well as a method of manufacturing the same.
2. Description of Related Art
In recent years, it has been highly demanded for miniaturization and reduction of electric power for terminals in a mobile communication system such as a portable telephone and, accordingly, a performance capable of attaining such miniaturization and reduction of electric power described above has also demanded for devices such as high frequency transistors used in the system. For example, with respect to power amplifiers for use in high frequency of 2 GHz band for digital cellulars having a leading position in current mobile communication, it has been demanded for devices capable that can operate on a single positive power source, can be driven at a lower voltage and at higher efficiency.
At present, a hetero junction field effect transistor (HFET) has been put to practical use as one of devices for high frequency power for use in high frequency power amplifiers in a microwave band and it is adapted to conduct current modulation utilizing hetero junction.
FIG. 5
shows an example for a constitution of HFET. In HFET, a first barrier layer
33
of AlGaAs mixed crystal, a channel layer
34
of InGsAs mixed crystal and a second barrier layer
35
of AlGaAs mixed crystal are laminated successively by way of a buffer layer
32
comprising a semi-insulative single crystals GaAs, and a gate electrode
40
is formed on the second barrier layer
35
.
Each of the first and the second barrier layers
33
,
35
has a carrier supply region containing n-type impurity
33
a
,
35
a
in high resistance region
33
b
,
35
b
respectively. When a voltage is applied to the gate electrode
40
, a drain current flowing between the source electrode
38
and the drain electrode
39
is modulated in accordance with the change of the applied voltage. Further, in HFET, as shown in
FIG. 5
, the thickness of the second barrier layer
35
generally is reduced near the gate electrode
40
as a recessed structure, so that a region in which carriers are depleted or carriers are reduced compared with other channel regions is formed in the region of the channel layer just below.
In the HFET having such a structure, since carriers are accumulated in the channel layer
34
by applying a positive voltage to the gate electrode
40
, it has a feature that the linearity of gate-source capacity Cgs and mutual conductance Gm to a gate voltage Vg is more excellent, in principle, compared with other devices, for example, junction FET (JFET) or Schottky junction FET (MES-FET: Metal Semiconductor FET). This can provide a significant advantage for improving the efficiency of power amplifiers.
Further, HFET of a structure as shown in
FIG. 6
has also been proposed recently. In this structure, p-type impurities are selectively diffused to a portion just beneath a gate electrode
60
, specifically, to a portion of a second barrier layer
55
corresponding to the recessed structure shown in
FIG. 5
, to form a p-type low resistance region
55
C (impurity concentration: 1×10
19
cm
−3
or higher). The p-type low resistance region
55
C is in contact with the gate electrode
60
and in the form of buried in the second barrier layer
55
.
In such a structure, since a PN junction is used, a built-in volt is increased and a large positive voltage can be applied to the gate electrode
60
, compared with a structure shown in
FIG. 5
using a Schottky junction for the gate electrode
40
. Accordingly, operation by a single positive power source can be facilitated while possessing excellent linearity of the mutual conductance Gm and the gate-source capacity Cgs of HFET as it is.
However, in the HFET structure in
FIG. 6
, the gate electrode
60
is in junction with the p-type low resistance region
55
C formed in the second barrier layer
55
. In a usual semiconductor of a large band gap (for example AlGaAs), it is difficult to obtain a satisfactory ohmic junction with the material for the gate electrode
60
used customarily (for example, a multi-layered structure: Ti/Pt/Au in view of the junction) compared with GaAs. As a result, the gate resistance is increased tending to cause degradation of high frequency characteristics.
In
FIG. 6
, elements
52
,
53
,
53
a
,
53
b
,
56
,
58
, and
59
correspond, respectively, to elements
32
,
33
,
33
a
,
33
b
,
36
,
38
, and
39
described above with reference to FIG.
5
.
SUMMARY OF THE INVENTION
The present invention has been accomplished in order to overcome such problems and an object thereof is to provide a semiconductor device which can operate easily with a single positive power source, and which is excellent in the linearity of mutual conductance Gm and source-gate capacity Cgs relative to gate voltage Vg.
Another object of the invention is to provide a compound semiconductor device for use in high frequency such as JFET or HEMT capable of avoiding degradation of high frequency characteristics by adopting satisfactory ohmic junction for the junction between the gate electrode and the p-type low resistance region, as well as a method for manufacturing such a semiconductor device.
The first invention of the present application provides a semiconductor device comprising a first semiconductor layer, a second semiconductor layer of a first conduction type formed in the first semiconductor layer, a third semiconductor layer of the first conduction type formed on the second semiconductor layer and an electrode film formed on the third semiconductor layer.
The second invention of the present application provides a semiconductor device comprising a semiconductor substrate, a buffer layer formed on the semiconductor substrate, a first barrier layer formed on the buffer layer, a channel layer formed on the first barrier layer, a second barrier layer formed on the channel layer, a second semiconductor layer formed on the first semiconductor layer in the second barrier layer, a third semiconductor layer formed on the second semiconductor layer and an electrode film formed on the third semiconductor layer.
Further, the third invention of the present application provides a method for manufacturing a field effect transistor comprising:
a step of forming a buffer layer on a semiconductor substrate,
a step of forming a first barrier layer on the buffer layer,
a step of forming a channel layer on the first barrier layer,
a step of forming a second barrier layer on the channel layer,
a step of forming a first semiconductor layer formed on the second barrier layer,
a step of forming an insulation film on the first semiconductor layer,
a step of aperturing the insulation film to form openings,
a step of forming a third semiconductor layer to the second semiconductor layer in the second barrier layer of the opening,
a step of forming a fourth semiconductor layer on the third semiconductor layer and
a step of forming an electrode film on the first semiconductor layer and the fourth semiconductor layer.
In accordance with the semiconductor device and the manufacturing method therefor of the present invention, a satisfactory ohmic junction can be formed, by forming the first low resistance region to the semiconductor layer, forming a second low resistance region in the first low resistance region, setting a band gap of the second low resistance region smaller than that of the first low resistance region and, further, depositing the electrode film.
Further, when such an ohmic junction is applied, for example, to JFET or HEMT, the gate resistance can be reduced remarkably.
REFERENCES:
patent: 5302840 (1994-04-01),
Loke Steven
Owens Douglas W.
Sonnenschein Nath & Rosenthal
Sony Corporation
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