Offsetting comparator device and comparator circuit

Details Offsetting comparator device and comparator circuit Offsetting comparator device and comparator circuit

1999-12-15

2002-01-15

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S103000, C327S065000, C327S563000, C327S053000

Reexamination Certificate

active

06339355

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to an offsetting comparator device for use in tristate level determination of a differential signal, i.e., which of the three conditions “0”, “1” and “Z” the signal assumes, for data communications purposes and so on. More particularly, the present invention relates to a technique of stabilizing the operation of the comparator device against a potential variation of the differential signal.
In a communications network, when the level of a differential signal should be determined as “0”, “1” or “Z”, an offsetting comparator device is used to see if the potential difference of the differential signal has exceeded an offset voltage.
FIG. 19
illustrates a tristate level determination of a differential signal in compliance with the IEEE 1394 standard. As illustrated in
FIG. 19
, the level of the differential signal is determined as “1” when the potential difference thereof is larger than 165 mV; “0” when the difference is smaller than −165 mV; and “Z” when the difference is in the range from −165 to 165 mV, both inclusive. Such a tristate level determination can be performed by connecting together a pair of comparator devices with an offset voltage of 165 mV and applying a voltage represented by the differential signal to the inverting input terminal of one of these comparator devices and to the non-inverting input terminal of the other.
FIG. 20
is a circuit diagram illustrating a conventional offsetting comparator device. In
FIG. 20
, a pair of p-channel transistors, which receive a differential input (C, D) with a fixed potential and supply currents I
3
and I
4
, respectively, is connected in parallel to another pair of p-channel transistors, which receive a differential input (A, B) and supply currents I
1
and I
2
, respectively. These currents I
1
, I
2
, I
3
and I
4
are combined at an output node so that a difference {(I
2
−I
1
)−(I
4
−I
3
)} between a sensed current corresponding to the potential difference represented by the differential input (A, B), i.e., (I
2
−I
1
), and an offset current, i.e., (I
4
−I
3
), is provided as output current to an external component. The potential difference of the differential input (A, B) when the sensed current (I
2
−I
1
) is canceled by the offset current (I
4
−I
3
) to bring the output current to zero is defined as “offset voltage”.
The known offsetting comparator device, however, has the following drawbacks.
FIG. 21
is a graph illustrating a relationship between an intermediate potential Vm of the differential input (A, B) and the magnitude of the current in the circuit shown in FIG.
20
. In
FIG. 21
, the potential difference represented by the differential input (A, B) is supposed to be constant and the potential represented by the differential input (C, D) is fixed as described above. Thus, the magnitudes of the currents I
3
and I
4
are kept substantially constant irrespective of the potential represented by the differential input (A, B), and therefore the offset current (I
4
−I
3
) is also substantially constant as shown in FIG.
21
.
However, even if the potential difference represented by the differential input (A, B) is constant, the magnitudes of the currents I
1
and I
2
are changeable with the potential variation. In Zone Za where the potential is larger than a potential obtained by subtracting a saturated drain-source voltage of the p-channel transistor from a supply potential, the magnitudes of the currents I
1
and I
2
are greatly variable with the potential represented by the differential input (A, B). In Zone Zb on the other hand, the transistors receiving the differential input (A, B) are not operable in their saturated regions anymore, but operate in a linear region. As a result, the sensitivity deteriorates, i.e., the sensed current (I
2
−I
1
) decreases. Thus, the offset voltage, i.e., the potential difference represented by the differential input (A, B) when the sensed current (I
2
−I
1
) is canceled by the offset current (I
4
−I
3
), is also greatly changeable with the potential represented by the differential input (A, B).
In general, the center potential of a differential signal is greatly changeable between a ground potential and a supply potential. Thus, an offsetting comparator device should always provide a constant offset voltage no matter where the center potential of the differential input is located within the range from the ground to supply potentials. Thus, if the offset voltage is greatly variable with the potential represented by the differential input as in Zones Za and Zb in
FIG. 21
, then serious problems are caused.
In addition, the characteristics of transistors included in the circuit are supposed to be non-changeable in the example illustrated in FIG.
21
. Actually, though, the transistor characteristics might be affected by supply voltage, temperature or process conditions. Thus, the relationship between the offset current (I
4
-I
3
) and sensed current (I
2
-I
1
) is even more complicated, thus further lowering the stability of the offset voltage.
According to a conventional technique, a level shifter is provided as preceding stage of the comparator to reduce the range of the potential supplied to the comparator to at least about a half of the supply voltage (see U.S. Pat. No. 5,424,657, for example). In such a configuration, if the differential input potential is higher than the center potential of the supply voltage, then the input potential is provided to the comparator after having been lowered by the level shifter. Alternatively, if the differential input potential is lower than the center potential of the supply voltage, then the input potential is provided to the comparator as it is. As a result, the variation range of the differential input potential is in effect one half of the supply voltage.
According to this configuration, however, just of Zones Za and Zb shown in
FIG. 21
can be eliminated and the problem cannot be solved radically. Also, if the differential input potential is changed by the level shifter, then the potential difference also increases albeit slightly, thus adversely affecting the stability of the offset voltage.
SUMMARY OF THE INVENTION
An object of the present invention is providing an offsetting comparator device that can obtain a constant offset voltage in spite of a potential variation of a differential signal.
Specifically, an offsetting comparator device according to the present invention determines whether or not a potential difference represented by a differential signal has exceeded an offset voltage. The device includes: a master comparator circuit, which receives the differential signal as differential input and supplies a sensed current corresponding to the potential difference represented by the differential input; and means for supplying an offset current. The device outputs a current representing a difference between the sensed and offset currents. The offset current supply means controls the magnitude of the offset current based on the potential level of the differential signal so as to stabilize the offset voltage.
According to the present invention, the magnitude of the offset current is controlled by the offset current supply means based on the potential level of the differential signal. Thus, even if the relationship between the potential difference represented by the differential input (or differential signal) and the sensed current has changed due to the potential variation of the differential signal, the magnitude of the offset current is controlled based on the potential represented by the differential signal. Accordingly, the offset voltage, which is a potential difference represented by the differential input when the sensed current is canceled by the offset current, does not change. As a result, a constant offset voltage can be obtained even if the potential represented by the differential signal has changed.
In one embodiment of the present invention, the offset curr

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