Offset trim using hot-electron induced VT-shifts

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control

Reexamination Certificate

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Details

C327S434000, C330S258000

Reexamination Certificate

active

06388494

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and apparatus for adjusting an offset voltage in an electronic circuit. More specifically, the present invention provides for altering a threshold potential of a transistor to adjust the offset voltage of the electronic circuit.
BACKGROUND OF THE INVENTION
Typical microelectronic systems have various electronic components that require matched transistor devices for various performance characteristics. Examples of applications of matched transistors include: current mirrors and differential input circuits, which are commonly found in operational amplifiers, comparators and other analog electronic circuits.
Metal Oxide Semiconductor (MOS) transistors are commonly used for integrating entire electronic systems on a single microchip (chip). Because digital and analog systems often coexist on the same chip, the overall performance of analog MOS systems are not always optimal. Conventional semiconductor processes are often optimized for small geometry devices due to the overwhelming demand for digital electronics with higher densities and lower costs.
Digital electronics do not require the same type of parameter optimization, as that required in analog electronics. For example, the resistivity of polysilicon may vary widely in a digital system. Since polysilicon is predominately used to form the gates of transistors, and/or to interconnect the gates of transistors, the absolute resistance is only of incidental importance. However, in analog electronic circuits, the resistivity of polysilicon may be used to form a resistor for compensating an ampifier's stability (i.e. a simple resistor capacitor pair used to cancel a pole in the frequency response characteristic of the amplifier). The variations in the resistivity could cause that amplifier to oscillate in an unstable condition. Since digital semiconductor processes are not optimized for analog characteristics, analog circuit designs are limited in performance.
Comparators are commonly used in analog to digital converter circuit (ADC). In a typical ADC (not shown), a digital to analog converter (DAC) is digitally controlled to produce an analog reference voltage. The analog reference voltage is compared (by a comparator) to the analog input signal to determine when a successful conversion has been reached. A least significant bit (LSB) of resolution in an ADC is a function of the full-scale voltage (V
FS
) and the number of bits of resolution (n) as given by V
LSB
=V
FS
/2
N
. However, a non-ideal comparator has an inherent input offset voltage characteristic that changes over process variations. A high input offset voltage, if not compensated for, will cause the ADC to lose resolution. For example, an ADC with a 2V fill-scale voltage and 10 bits of resolution has an LSB equivalent to 1.953 mV. If the input offset voltage of the comparator exceeds the LSB criteria, then the comparator may not be able to discern an LSB of analog input signal.
SUMMARY OF THE INVENTION
In accordance with the invention, the above and other problems are solved by an apparatus for adjusting an offset between a first MOS transistor and a second MOS transistor. A measurer is employed to measure the offset between the MOS transistors; and a selector selects one of the MOS transistors based upon the measured offset. A threshold shifter increases the threshold voltage of the selected MOS transistor by injecting charge into its oxide layer so that the offset is optimized for use in an electronic circuit.
In accordance with other aspects of the invention, the offset between the first MOS transistor and the second MOS transistor represents at least a threshold voltage mismatch or a drain current mismatch. Also, a detector is used to determine when the electronic circuit is in a mode to adjust the offset and another mode for operating the electronic circuit.
In accordance with another embodiment of the invention, an apparatus adjusts an offset between a first MOS transistor and a second MOS transistor in an electronic circuit. A measurer is employed to measure an output of the electronic circuit; and an analyzer to determine the offset between the first MOS transistor and the second MOS transistor based on the measured output. A selector selects one of the MOS transistors based upon the offset. A threshold shifter increases the threshold voltage of the selected MOS transistor by injecting charge into its oxide layer so that a value of the offset between the first MOS transistor and the second MOS transistor is adjusted to another value that is optimized for use in an electronic circuit.
In accordance with other aspects of the invention, the electronic circuit is a differential amplifier with an output and a differential pair input stage. A gate of the first MOS transistor is a first input node and a gate of the second MOS transistor is a second input node for the differential pair input stage.
In accordance with still other aspects of the invention, a switching device is coupled to a drain of the selected MOS transistor when activated by the selector so that the selected MOS transistor is activated in hard saturation and hot charge carriers are injected into its oxide layer and the threshold voltage of the selected MOS transistor shifts.
In accordance with yet other aspects of the invention, the selector includes the differential pair so that a differential input voltage is applied between the first input node and the second input node to select one of the MOS transistors.
In accordance with still further aspects of the invention, the electronic circuit is a converter having a first current source that includes the first MOS transistor and a second current source that includes the second MOS transistor. A switching device is coupled to a current source that includes the selected MOS transistor when activated by the selector so that the selected MOS transistor is activated in hard saturation, hot change carriers are injected into its oxide layer and the threshold voltage of the selected transistor shifts. The selector controls the first current source with a first control bit and the second current source with a second control bit. The offset is determined by measuring an output of the converter and the converter can be a digital to analog converter.
In accordance with yet other aspects of the invention, the other value of the offset (after adjustment) can be less tan the value of the offset (before adjustment). Alternatively, when the electronic circuit is a comparator, the other value for the offset (after adjustment) can be greater than the value of the offset (before adjustment).
In accordance with another embodiment of the invention, a method for adjusting an offset in an electronic circuit by measuring a difference between a first threshold voltage for a first MOS transistor and a second threshold voltage for a second MOS transistor. The measured difference is employed to produce a measured offset that is compared to a tolerance value. The value of at least one of the first threshold voltage and the second threshold voltage is shifted based on the comparison of the measured offset to the tolerance value.
In accordance with other aspects of the invention, the threshold voltage of the first MOS transistor and the second MOS transistor are measured. The difference between the first threshold voltage and the second threshold voltage is determined and employed to produce the measured offset.
In accordance with still other aspects of the invention, one of the first MOS transistor and the second MOS transistor is elected based on the comparison of the measured offset to the tolerance value. The absolute drain to source voltage of the selected MOS transistor is adjusted so that the selected MOS transistor will be in hard saturation when active. The selected MOS transistor is activated over a time interval so that the selected MOS transistor will be placed in hard saturation, charge carriers will be injected into the oxide layer of the selected MOS transistor over the time interval and a thr

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