Offset trim circuit and method for a...

Details Offset trim circuit and method for a... Offset trim circuit and method for a...

2007-01-30

2007-01-30

Nguyen, Khank Van (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S009000, C330S255000, C330S258000

Reexamination Certificate

active

10716019

ABSTRACT:
A constant-transconductance rail-to-rail CMOS input circuit with offset trim is provided. PMOS and NMOS differential trim stages are scaled versions of PMOS and NMOS input stages respectively. The differential trim stages are configured to adjust the offset of the differential output current with accuracy over temperature. A first current mirror circuit is configured to receive a fraction of a bias current (βI), where β is related to the input common mode voltage. A second current mirror circuit is configured to receive another fraction of the bias current ((1−β)I). The first current mirror circuit is configured to provide current βI to the PMOS input stage, and a scaled-down version of current βI to the PMOS differential trim stage. The second current mirror circuit is configured to provide current ((1−β)I) to the NMOS input stage, and a scaled-down version of current ((1−β)I) to the differential PMOS trim stage.

REFERENCES:
patent: 4618833 (1986-10-01), Russell
patent: 4797631 (1989-01-01), Hsu et al.
patent: 6194962 (2001-02-01), Chen
patent: 6696894 (2004-02-01), Huang

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