Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-03-27
2003-12-16
Berhane, Adolf D. (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S285000
Reexamination Certificate
active
06664774
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to voltage regulator circuits. More particularly, the invention relates to offset peak current mode control for multiple-phase DC-to-DC switched mode power converters.
2. Description of Related Art
Switched mode DC-to-DC power converters are commonly used in the electronics industry to convert an available direct current (DC) level voltage to another DC level voltage. A switched mode converter provides a regulated DC output voltage by selectively storing energy by switching the flow of current into an output inductor coupled to a load. A synchronous buck converter is a particular type of switched mode converter that uses two power switches, such as MOSFET transistors, to control the flow of current in the output inductor. A high-side power switch selectively couples the inductor to a positive power supply while a low-side power switch selectively couples the inductor to ground. A pulse width modulation (PWM) control circuit is used to control the gating of the high-side and low-side power switches. Switched mode power converters generally offer high efficiency and high power density, particularly when MOSFET devices are used for the power switches due to their relatively low on-resistance. Therefore, switched mode power converters are used to provide power to electronic systems having demanding power requirements, such as microprocessors that require a control voltage (Vcc) of 1 to 1.5 volts with current ranging from 40 to 60 amps.
For certain applications having especially high current load requirements, it is known to combine plural switched mode power converters together in multiple-phase configurations operated, in an interleaf mode. Each individual switched mode power converter of the multiple-phase power converter operates during a portion of the power cycle, so that there are multiple power pulses per cycle. As a result, the interleaved multiple-phase power converter can produce more power than can the individual single-phase power converters. Another advantage of interleaved operation is that the output current ripple across the load is effectively reduced, thereby enabling the use of smaller filter capacitors to eliminate the current ripple. Thus, multiple-phase power converters can be smaller, lighter, and less costly than single-phase power converters.
It is necessary to regulate the performance of a switched mode power converter in order to protect the load from damage caused by excessive current, ensure that sufficient current is delivered to the load in view of changing load conditions (i.e., controlling voltage “droop” caused by a step load), and permit current sharing between phases of multi-phase converters. In current-mode regulation, a first feedback loop senses the output voltage and a second feedback loop senses the current delivered to the load. The first feedback loop compares the output voltage to a reference to derive a voltage error signal. The second feedback loop provides a voltage proportional to the sensed current. The voltage error signal is compared with the current sense signal by the PWM circuit to thereby control the duty cycle that determines the on time of the power switches. The voltage error signal can be proportional to the intra-cycle peaks of the sensed current (known as peak current control), or can be proportional to the average value of the sensed current (known as average current control).
In a switched mode converter, the average inductor current is higher at a low DC input voltage than it is at a high DC input voltage, thereby requiring longer on-time of the power switches to achieve the same output power when a low DC input voltage is utilized. This phenomenon precludes the use of peak current control with multiplephase power converters if the longer on-times result in an overlap of the duty cycles applied to the separate phases. For example, such an overlap may occur with a three-phase converter having a relatively low input voltage (e.g., 5 volts or less) in which the duty cycle applied to each phase is increased beyond 33%. The overlap causes the current sense signal to become distorted at the peak portion so that a clean comparison between the current sense signal and the voltage error signal cannot be obtained.
Accordingly, it would be desirable to provide current mode control for a multiple-phase power converter operated with a relatively low input voltage or a relatively high duty cycle. More specifically, it Would be desirable to provide current mode control of a multiple-phase power converter that utilizes information from the clean (i.e., non-overlapping) portion of the current sense signal.
SUMMARY OF THE INVENTION
The present invention provides an offset peak current mode control circuit for use with a multiple-phase DC-to-DC voltage converter. When the DC-to-DC voltage converter is operated with a relatively low input voltage or a relatively high duty cycle resulting in an overlap of the current sense signal, the offset peak current mode control circuit utilizes information from the clean (i.e., non-overlapping) portion of the current sense signal, and then stretches the duty cycle applied to an associated voltage converter module so that it extends into the time of the overlapping portion of the current sense signal.
In an embodiment of the invention, a multiple-phase DC-to-DC voltage converter comprises a plurality of converter modules connected to a common load and having a common input voltage source. A current sensor is coupled to a sensing resistor disposed in series between the common input voltage source and the load to derive a current sense signal corresponding to current passing through the sensing resistor. A voltage error sensor is coupled to the load to derive a voltage error signal corresponding to difference between an output voltage of the voltage converter and a reference voltage. A current mode control circuit is connected to each respective one of the plurality of converter modules. The current mode control circuits receive the current sense signal and the voltage error signal, and provide gate driving signals to the respective converter module having a duty cycle determined by the current sense signal and the voltage error signal. A phase select circuit is coupled to the current mode control circuits and alternately provides the current mode control circuits with a phase select signal to initiate successive phases of operation Within a power cycle. When there is an overlap between adjacent ones of the successive phases, the current mode control circuits are operative to compare the current sense signal and the voltage error signal during a non-overlapping portion of a phase, and stretch a duration of the duty cycle of the gate driving signals to extend at least partially into an overlapping portion of the phase.
Another embodiment of the invention provides a method for providing offset peak current mode control of one of a plurality of converter modules of a multiple-phase DC-to-DC voltage converter when there is an overlap between adjacent phases of operation of the plurality of converter modules. The multiple-phase DC-to-DC voltage converter comprises a plurality of converter modules connected to a common load and having a common input voltage source. A first step of the method includes sensing output current delivered to the common load to thereby determine a current sense signal representative of the current. The current sense signal includes a clean portion prior to the overlap and a distorted portion during the overlap. A second step includes sensing output voltage across the common load to thereby determine a voltage error signal representative of a difference between the output voltage and a reference. A third step includes comparing the current sense signal with the voltage error signal during the clean portion of the current sense signal to thereby generate an intermediate gate-driving signal. A fourth step includes stretching the intermediate gate-driving signal to provide a final gate drive signal. A
Berhane Adolf D.
O'Melveny & Myers LLP
Semtech Corporation
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