Offset-insensitive switched-capacitor gain stage

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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Details

341143, H03M 302

Patent

active

053631021

ABSTRACT:
An IC chip formed with an analog-to-digital converter having a switched-capacitor programmable gain stage and employing a switched-capacitor sigma-delta modulator. The chip includes pins to receive a number of different audio input signals which are selectively connectible to buffer amplifiers the outputs of which are directed to a switch to select one output for further processing. The selected buffer amplifier output is d-c coupled to an input signal terminal of a switched-capacitor programmable gain stage. The output of this gain stage is coupled to an output stage including an op-amp and associated switched-capacitor circuitry. The programmable gain stage has a reference input terminal which is connected through an IC chip pin to an external capacitor the other electrode of which is returned to signal common. This capacitor develops a d-c voltage corresponding to the offset voltages of the operative buffer amplifier and the op-amp, and including a component corresponding to charge-injection from MOS switches. Absorption of such d-c voltages by this capacitor prevents those voltages from being significantly gained by the amplifier circuitry, and thereby prevents those voltages from using up an excessive portion of the dynamic range of the circuitry.

REFERENCES:
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patent: 5148167 (1992-09-01), Ribner
patent: 5177484 (1993-01-01), Bruckmann
patent: 5220286 (1993-06-01), Nadeem

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