Offset insensitive hysteresis limiter

Details Offset insensitive hysteresis limiter Offset insensitive hysteresis limiter

1997-10-22

1999-08-03

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Unwanted signal suppression

327307, H03B 100, H03L 500

Patent

active

059330520

ABSTRACT:
An offset-free switched capacitor circuit selectively operated by a non-overlapping two-phase clock signal for processing a frequency shift keying (FSK) input signal is provided. The switched capacitor circuit includes a filter which inputs a voltage signal for generating an output signal which assumes a first voltage value Vt1 at the first phase of the clock signal and assumes a second voltage value Vt2 at the second phase of the clock signal. The output signal of the switched capacitor circuit is an input to a succeeding hysteresis limiter. The hysteresis limiter, which receives the difference of Vt2 and Vt1, is operative to generate a logic signal which is HIGH when an input signal thereof exceeds a HIGH.sub.-- ref signal and is LOW when the input signal thereof falls below a LOW.sub.-- ref signal, and is so operated that the offset voltage associated with the amplifier therein is counterbalanced via internal operation.

REFERENCES:
patent: 4492927 (1985-01-01), Holberg
patent: 4543534 (1985-09-01), Temes et al.
patent: 4616145 (1986-10-01), Myers
patent: 4745594 (1988-05-01), Takahashi
patent: 5124593 (1992-06-01), Michel
patent: 5166632 (1992-11-01), MacKenzie
patent: 5659269 (1997-08-01), Myers
patent: 5774004 (1998-06-01), Peng

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