Offset correction circuit for a sigma-delta coding device

Details Offset correction circuit for a sigma-delta coding device Offset correction circuit for a sigma-delta coding device

1988-10-07

1990-01-30

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 27, 341143, H04B 1404

Patent

active

048978566

ABSTRACT:
An offset correction circuit is disclosed in a digital-to-analog coder (10) comprising a delta coder (18) providing a serial bit string at a high frequency F in response to digital words supplied at a low frequency F, and an analog integrator (22) providing an analog output signal (24) which is an analog representation of the digital words. The offset correction circuit avoids introducing an offset in the analog output of the integrator (22) when a PLO correction is taken to slow down or to speed up the clock controlling the input of the digital words. Such a circuit is implemented by a state generator which provides a corrected pulse in place of the sigma-delta data which lasts half the duration of the offset.

REFERENCES:
patent: 4039955 (1977-08-01), Eggermont et al.
patent: 4209773 (1980-06-01), Everard
patent: 4528551 (1985-07-01), Agrawal et al.

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