Amplifiers – With periodic switching input-output
Reexamination Certificate
2001-12-31
2003-12-02
Nguyen, Patricia (Department: 2817)
Amplifiers
With periodic switching input-output
C330S011000, C327S307000
Reexamination Certificate
active
06657488
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to amplifier circuits and more particular to offsets associated with amplifiers.
2. Description of the Related Art
FIG. 1
shows the block diagram of a typical high-speed optical receiver
100
, designed to work at rates of, e.g., 2.7 GHz. The received optical energy
101
is converted to a current using a photodiode,
103
. The photodiode signal current I
o
is converted to a voltage using the transimpedance amplifier (TIA)
105
. The signal at the output of TIA
105
is small for low optical energy signals, and can contain significant corruption due to, e.g., noise and limited rise and fall times. The typical range of signal amplitude at the output of the TIA
105
is from a few millivolts to a few hundred millivolts. TIA
105
is followed by additional gain, usually implemented with a limit amplifier or an automatic gain control (AGC) amplifier
107
. Note that although
FIG. 1
shows a fully differential system, it is common for some of the illustrated signals, e.g., Io, V
1
, V
2
or the clock and data outputs, to be single ended, and the principles described herein are still applicable.
The function of the limit amplifier is to produce a consistent waveform from the TIA output, which can be used by a clock and data recovery circuit (CDR)
109
, irrespective of the incoming optical energy. The clock and data recovery circuit
109
recovers both the data and the clock typically embedded in the input data stream received by the photodiode D
1
and provides differential clock and data signals
111
and
113
, respectively.
If amplifier
107
is implemented as a limit amplifier, adequate gain is provided to create a full swing output from the minimum desired input signal. For larger input signals, the output does not increase significantly, however the output signal will be improved in regards to deterministic jitter and noise performance. If amplifier
107
is implemented as an AGC amplifier, the output signal strength is detected, and the gain is adjusted to provide optimal signal strength at the output for a wide range of input signal levels. In the case of a small input signal, the AGC gain will be large, comparable to the gain of a limit amplifier receiving a small signal in the same application. For larger signals, the AGC circuitry will reduce the gain to maintain the desired output signal strength, keeping the amplifier out of saturation. A larger signal will produce a better signal at the output of the AGC, since circuit non-idealities such as input-referred offset and noise become less significant.
FIGS. 2A
shows exemplary output from the TIA amplifier
105
.
FIGS. 2B and 2C
show respectively the expected outputs for a limit amplifier and an AGC amplifier for the input signal shown in
2
A.
FIG. 2B
a shows that the limit amplifier is driven to the maximum output swing (+/−0.5V). Though it preserves the data values and zero crossings, it does not preserve the shape of the input signals due to the non-linear limiting function.
FIG. 2C
shows that the AGC amplifier gain is set at a level to produce an output that is more linearly related to the input.
An AGC amplifier is implemented by detecting the signal strength at some point in the amplifier. This signal is used in a negative feedback loop to control the gain of the amplifier so that an optimal output signal is produced. Implementation of a high-speed AGC amplifier in a CMOS process presents many challenges. One reason for this is that a high quality diode is not readily available in a standard CMOS process. The diode facilitates rectification of the signal for amplitude detection. Though a similar function can be implemented using MOS devices, the circuit non-idealities and limited bandwidth of the devices make amplitude detection difficult. In a high speed bipolar process, accurate signal detection is feasible to provide the feedback signal for the AGC amplifier. Because the recovery of a bipolar device from an overdrive (saturation) can be slow, an AGC amplifier is more desirable for a bipolar process.
The limit amplifier or AGC amplifier often has two other functions associated with it: offset correction and slice level adjustment. An undesired offset in the amplifier can prevent the proper detection of small signals and random amplifier offsets, due to mismatch between critical devices, become greater with smaller device sizes. For a gigahertz CMOS limiting amplifier optimized for maximum gain and bandwidth, device sizes are relatively small and offsets on the order of the amplifier sensitivity (the minimum input peak to peak voltage) are not uncommon. That makes it necessary to include circuitry that senses the amplifier offset and cancels it. The offset correction is often implemented with the use of negative feedback from the amplifier's output.
In some communication systems, such as those that operate in accordance with the Synchronous Optical Network (SONET) standard, scrambling and other techniques ensure that over the long term there will be a nearly equal amount of ones and zeros received by the data processing system. In such a system, desired offset correction can be implemented conceptually with the feedback system illustrated in FIG.
3
. The offset is represented by the voltage V
off
, which is shown as entering summing node
303
. A sense circuit
301
detects any deviation from this equality, i.e., the amplifier offset. A trim circuit
305
, which is coupled to summing node
307
, can utilize the output of the sense circuit
301
to trim the offset.
Since the data equality holds only over a long period of time, the sensing circuitry should have a very low bandwidth. If not, the offset correction signal that is fed back can become a jitter mechanism. Many existing offset correction systems employ a purely analog approach, which makes realization of this low bandwidth only possible with large external passive devices. That results in extra pins on the integrated circuit being devoted to connecting these passive devices. However, the available number of pins can be limited on integrated circuits such as those implementing clock and data recovery circuits, and extra pins can result in bigger packages and thus bigger component costs. Not only do passive devices cost both board area and adversely affect component cost, their use brings a very sensitive node out of the chip, where great care should be taken to shield it from unwanted noise sources.
Another function that may be implemented by the amplifier stage
107
(see
FIG. 1
) is to provide an adjustable slicing level to compensate for the asymmetric noise characteristic present in the photodiode output. Slicing level is defined as the threshold voltage where an incoming signal is determined to be either a “1” bit or a “0” bit. The need for an adjustable slicing level can be seen by looking at the photodiode output current or the TIA output voltage shown in FIG.
2
A. At low levels of optical energy (corresponding to a zero level bit for example), the noise current is low. At higher levels of optical energy (corresponding to a one-level bit), the noise current may be higher. This asymmetry, as shown in
FIG. 2A
, may require an introduction of an intentional offset to create the most reliable output. As shown in
FIG. 2A
, a slicing level of zero gives a smaller amount of margin for the positive swing compared to the negative swing. If the threshold is set to roughly −2 mV in the case shown, the margin is more symmetric and better results are to be expected. Thus, introducing a small offset serves to optimize noise margin and signal strength.
FIG. 4
illustrates the concept of introducing a slice voltage at summing node
401
.
Some systems employ a closed-loop approach to dynamically adjust the slicing voltage. Some metric for system performance is monitored and the slicing voltage is adjusted accordingly. In this case, the amplifier offset is unimportant. Other systems may require that the slicing voltage remain at a fixed, repeatable level.
King Eric T.
Pastorello Douglas F.
Perrott Michael H.
Nguyen Patricia
Silicon Laboratories Inc.
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