Coded data generation or conversion – Phase or time of phase change – Synchro or resolver signal
Reexamination Certificate
1999-01-12
2001-04-10
Young, Brian (Department: 2819)
Coded data generation or conversion
Phase or time of phase change
Synchro or resolver signal
C341S111000
Reexamination Certificate
active
06215426
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an encoder for use in position detection of a motor or a linear encoder used in an NC machine tool or an industrial robot, and specifically to an offset correcting circuit for compensating an offset in an encoder.
DESCRIPTION OF THE RELATED ART
As a method of obtaining a moving amount of a movable body as an angular amount, there is known a method in which a moving amount of the movable body is first detected by a position detector as an analog value in the form of a sine wave, a cosine wave or the like, then the detected analog value is converted to a digital value, and then the digital value is converted to an angular amount by an encoder.
The position detector detects A-phase and B-phase signals which are two signals of different phases in order to improve resolution. The two signals of different phases are converted by analog-digital converters to digital signals, respectively, and an angle is computed based on the digital signals. If the zero level of a sine or cosine wave detected by the position detector shifts and an offset is produced, the detected angular amount involves an error.
FIGS. 8
a
to
8
j
are diagrams for explaining an offset produced at an encoder.
FIGS. 8
a
to
8
e
relate to the case where an offset is not produced, and
FIGS. 8
f
to
8
j
relate to the case where an offset is produced. In
FIGS. 8
a
and
8
b
, when the zero level is taken as a threshold, a rectangular pulse PA is formed from the A-phase signal (
FIG. 8
c
), and a rectangular pulse PB is formed from the B-phase signal (
FIG. 8
d
). Each time the rectangular pulse rises or falls, increment or decrement is effected at a position counter (
FIG. 8
e
). If the zero level does not shift and an offset is not produced and if a movable body is doing a uniform motion, duty factors of the rectangular pulses PA, PB are both 50%.
In contrast thereto, as shown in
FIGS. 8
f
and
8
g
, if the zero level shifts and an offset is produced (as indicated by a broken line), duty factors of the rectangular pulse PA (
FIG. 8
h
) and the rectangular pulse PB (
FIG. 8
i
) deviate from 50% to a large extent, and timing of increment or decrement at the position counter shifts in the forward or backward direction even if a movable body is doing a uniform motion. An error in position detection caused by such an offset has a large influence through an interpolation performed for improving the resolution.
As a conventional method for correcting the offsets of the A-phase and B-phase signals, there is known a method in which a difference between each of the A-phase and B-phase signals and a signal having a phase by 180° different from the phase of each signal is regulated by an adjustable resistor to thereby correct the offset.
This method of correcting the offset has problems in that it requires a process of adjusting the adjustable resistor, and in that handling thereof is troublesome. Further, even after such regulation, an offset may be again produced due to a difference in age deterioration between elements. It is possible, but actually difficult, to regulate the offset again by the adjustable resistor.
As another method of correcting the offset, it is conceivable to remove a direct-current component by AC coupling. This method has, however, a problem that the offset correction cannot be performed when a movable body stops and frequencies of the A-phase and B-phase signals are both “0”.
In order to solve the above problems, there has been proposed a method in which an average of positive and negative values which one of the A-phase and B-phase signals takes when the other crosses zero is obtained to thereby correct the offset (for example, Japanese Patent Preliminary Publication No. Hei 1-92612). According to this method of correcting the offset, in the case shown in
FIGS. 9
a
and
9
b
, the offset correction value for the A-phase signal is an average (V
2
+V
4
)/2 of a positive value V
2
and a negative value V
4
which the A-phase signal takes when the B-phase signal crosses zero, and the offset correction value for the B-phase signal is an average (V
1
+V
3
)/2 of a positive value V
1
and a negative value V
3
which the B-phase signal takes when the A-phase signal crosses zero. The offset correction can be performed by an offset correcting circuit having structure as shown in FIG.
10
.
The conventional offset correcting circuit shown in
FIG. 10
has a detection timing computing element
20
for detecting the time when one of the A-phase and B-phase signals crosses zero and determining the time when a value of the other of the signals is to be detected, an A-phase offset detector
20
A and a B-phase offset detector
20
B for executing the above computation using positive and negative digital values sampled in accordance with detection timing determined by the detection timing computing element
20
to thereby detect an offset correction value, an A-phase subtracter
21
A for subtracting an A-phase offset correction value from an A-phase digital signal to thereby obtain an offset-corrected value, a B-phase subtracter
21
B for subtracting a B-phase offset correction value from a B-phase digital signal to thereby obtain an offset-corrected value, and an angle detecting circuit
23
for detecting an angle based on the offset-corrected A-phase and B-phase signals.
The above described conventional offset correction circuit has a problem in that when the sampling period is long relative to the input frequency, it takes time to obtain a value which is to be sampled at the time of zero-crossing, and therefore, it takes time to obtain an offset correction value. This hinders obtaining a correct offset correction value.
FIGS. 11
a
to
11
c
,
12
a
to
12
c
and
13
a
to
13
e
are diagrams for explaining the relation between zero-crossing and sampling in the conventional offset correcting circuit.
FIGS. 11
a
to
11
c
relate to the case where a value can be sampled at the time of zero-crossing, and
FIGS. 12
a
to
12
c
relate to the case where a value can not be sampled at the time of zero-crossing. In the case of
FIGS. 11
a
to
11
c
where zero-crossing occurs corresponding to a sampling point of time, among the values (points in
FIG. 11
a
) of the A-phase signal sampled in accordance with a clock signal (
FIG. 11
c
), a sampled signal value V
2
corresponding to zero-crossing of the B-phase analog signal (
FIG. 11
b
) can be used as one of the values required for computing an offset value.
In contrast thereto, in the case of
FIGS. 12
a
to
12
c
where zero-crossing occurs not corresponding to a sampling point of time, there is no signal value sampled corresponding to zero-crossing of the B-phase analog signal (
FIG. 12
b
) among the values (points in
FIG. 12
a
) of the A-phase signal sampled in accordance with a clock signal (
FIG. 12
c
). Therefore, a value required for computing an offset value cannot be obtained at this time.
Therefore, in the case shown in
FIGS. 13
a
to
13
e
, because of the necessity of correspondence between a sampling point and the B-phase analog signal's zero-crossing (
FIG. 13
b
), it takes time longer than the interval of zero-crossing to obtain values V
2
and V
4
which can be used for computing an offset value among the sampled values of the A-phase signal (
FIG. 13
a
), as shown in
FIGS. 13
c
and
13
d
. Therefore, it takes a long time to obtain an offset correction signal (V
2
+V
4
)/2, and therefore, a correct offset value cannot be obtained.
Further, detection of voltages of the A-phase and B-phase signals for obtaining an offset value is normally performed only once, and the detected voltage changes to a large degree in the presence of noise. Therefore, there is also a problem that the influence of noise on the offset value is serious.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an offset correcting circuit which can detect a correct offset value even when a sampling period is long as in the case of a low-speed A/D converter or the like. Another objec
Inoue Tadashi
Taniguchi Mitsuyuki
Fanuc Ltd.
Nguyen John
Staas & Halsey , LLP
Young Brian
LandOfFree
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