Coded data generation or conversion – Converter compensation
Reexamination Certificate
2000-04-06
2002-04-23
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000, C341S155000
Reexamination Certificate
active
06377195
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a method and to an arrangement according to the preambles of respective independent claims
1
and
4
.
BACKGROUND OF THE INVENTION
The digitalisation of an analogue signal requires the use of an analogue-digital converter. High sampling speeds are required to convert a real time analogue signal to a digital format. One way of achieving the requisite sampling speed in real time conversion is to use so-called parallel analogue-digital converters.
An example of one such parallel analogue-digital converter is described in U.S. Pat. No. 5,585,796.
One problem with this type of analogue-digital converter is that the individual analogue-digital conversion channels have mutually different offsets. A parallel analogue-digital converter including several time multiplexed channels where each channel has a unique offset gives rise to undesirable frequency components in an output signal from such an analogue-digital converter.
This has been solved with an analogue offset compensation of the type correlated double-sampling as described in “A 10-bit 5MS/s successive approximation ADC cell used in a 70MS/s ADC array in 1.2 &mgr;m CMOS”, IEEE Journal of Solid State Circuits, Vol. 29, No. 8, pp. 866-872, Aug. 1994, J. Yuan and C. Svensson.
The drawback with this technique is that the analogue offset compensation takes a certain amount of time to put into effect, in this case four clock periods, therewith increasing the time required by a channel for conversion.
SUMMARY OF THE INVENTION
The present invention addresses the aforesaid problems by providing a method for offset compensation in parallel channel analogue-digital converters according to claim
1
, and a parallel channel analogue-digital converter according to claim
4
.
The object of the present invention is to provide a method of digital offset compensation which will at least reduce the aforesaid problems.
In this regard, one particular object of the present invention is to provide a method of offset compensation in parallel channel analogue-digital converters in which the offset to be compensated can be allowed to be large without having an effect on the signal to noise ratio of the output signal.
One advantage with the present invention is that the analogue components in the analogue-digital converter influencing the offset can be made with relatively poor precision without influencing the precision of the output signal.
Another advantage with the present invention is that the method can be easily implemented.
A preferred embodiment of the invention has the advantage of enabling the offset to be removed by subtracting a mean value of the output signal from the analogue-digital converter for each channel, therewith enabling the offset to be large.
REFERENCES:
patent: 4633226 (1986-12-01), Black, Jr.
patent: 4994805 (1991-02-01), Dedic
patent: 5272481 (1993-12-01), Sauer
patent: 5459464 (1995-10-01), Bénéteau et al.
patent: 5585796 (1996-12-01), Svensson et al.
patent: 5675334 (1997-10-01), McCartney
patent: 6137431 (2000-10-01), Lee et al.
patent: 99/34517 (1999-07-01), None
Jiren Yuan et al., IEEE Journal of Solid State Circuits, vol. 29 No. 8, Aug. 1994, pp. 866-873 “A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2-&mgr;m CMOS”.
Eklund Jan-Erik
Gustafsson Fredrik
Burns Doane Swecker & Mathis L.L.P.
Telefonaktiebolaget LM Ericsson (publ)
Williams Howard L.
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