Amplifiers – With periodic switching input-output
Reexamination Certificate
2003-01-09
2004-06-15
Shingleton, Michael B (Department: 2817)
Amplifiers
With periodic switching input-output
C330S051000, C330S253000, C330S258000
Reexamination Certificate
active
06750704
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to comparator circuits and, more particularly, to a stable, high-speed, high-gain, differential amplifier suitable for use as a comparator preamplifier and utilizing separately driven load devices for offset-voltage compensation.
BACKGROUND OF THE INVENTION
As modern communication receiver functions migrate further into the more cost-effective digital domain, there is an increasing need for wide-bandwidth analog-to-digital converters (ADCs). One promising ADC architecture, known as a multi-bit sigma-delta modulator, typically utilizes an internal flash ADC incorporating a large array of comparators and preamplifiers. The performance of the multi-bit sigma-delta ADC can be significantly impacted by the design characteristics (e.g. offset-voltage, gain, common-mode stability, input capacitance) of the flash preamplifiers.
For example, variations in the integrated circuit fabrication process can cause mismatches in the input devices which process the amplifier's input signals. This results in an offset-voltage which is generally defined as the input voltage required to drive the preamplifier's output voltage to zero. Offset-voltages in the preamplifiers of a flash ADC will result in a nonlinear ADC transfer function. When used in a high-bandwidth multi-bit sigma-delta modulator, this nonlinear transfer function will cause distortion in the overall ADC and thus reduce its resolution.
In a comparator, the preamplifier is typically followed by a clocked latch that samples the preamplifier's output signal and produces a full logic-level output. CMOS latches for example, often have large offset-voltages relative to the preamplifier, the impact of which is reduced if the gain of the preamplifier is high. Thus, a large preamplifier gain is desirable.
The comparator latch should be designed utilizing fully differential circuitry for noise rejection and low offset-voltage. This requires a fully differential preamplifier utilizing common-mode feedback to maintain the preamplifier's outputs at a stable voltage between the power supply voltages. Ideally, the common-mode feedback circuitry should not degrade the gain or offset performance of the preamplifier.
Finally, the number of preamplifier's utilized in a flash ADC increases with resolution. The preamplifier array is typically driven by an on-chip operational amplifier. Thus, the preamplifier should have a low input capacitance in order to minimize power dissipation in the operational amplifier.
One known offset-cancellation technique characterized by high preamplifier gain and low input capacitance utilizes a dual differential amplifier wherein the output is simply the sum of amplified versions of two differential input signals. This dual differential amplifier operates in two phases, an offset-cancellation phase and an amplification phase. During the offset-cancellation phase, the input terminals are coupled together or to a common voltage, and feedback is applied to auxiliary input terminals. The voltage that is required to force a zero output voltage is stored on capacitors coupled to the auxiliary input terminals. This stored voltage reduces offset-voltage during a subsequent amplification phase when the input terminals are coupled to receive a differential input signal. Unfortunately, such designs typically utilize a differential pair to realize the auxiliary input thus resulting in more current drain in the preamplifier. For more information, the interested reader is referred to U.S. Pat. No. 4,628,274 issued Dec. 9, 1986 and entitled “Amplifier with Input Drift Voltage Compensation” and U.S. Pat. No. 5,311,085 issued May 10, 1994 and entitled “Clocked Comparator with Offset-Voltage Compensation”.
Another technique utilizes the amplifier's load devices as the auxiliary inputs thus saving power. Examples of such arrangements are shown in U.S. Pat. No. 5,017,805 issued May 21, 1991 and entitled “Offset Cancel Latching Comparator”, U.S. Pat. No. 5,565,813 issued Oct. 15, 1996 and entitled “Apparatus for a Low Voltage Differential Amplifier Incorporating Switched Capacitors”, and in “A Fully Differential Comparator Using a Switched-Capacitor Differencing Circuit with Common-Mode Rejection”, IEEE Journal of Solid-State Circuits, Volume 32, No. 2, pages 250-253, Feb. 1997. Unfortunately, techniques utilizing this approach cannot achieve high gain without sacrificing common-mode stability and requiring large capacitor values.
It should be therefore appreciated that it would be desirable to provide an improved offset-compensated amplifier that is characterized by superior common-mode stability without a corresponding sacrifice in differential gain.
REFERENCES:
patent: 4628274 (1986-12-01), Vittoz et al.
patent: 4710724 (1987-12-01), Connell et al.
patent: 5017805 (1991-05-01), Kase
patent: 5311085 (1994-05-01), Pelgrom et al.
patent: 5565813 (1996-10-01), Connell et al.
patent: 6046638 (2000-04-01), Hogeboom
patent: 5175744 (1993-07-01), None
Baghai et al. “A New Offset Cancellation Technique for CMOS Differential Amplifiers” IEEE Journal of Electronics 1995 pp 2229-2232.*
Tanchy Shih, Lawrence Der, Stephen H. Lewis, and Paul J. Hurst, “A Fully Differential Comparator Using a Switched-Capacitor Differencing Circuit with Common-Mode Rejection”, IEEE Journal of Solid-State Circuits, Feb. 1997, pp. 250-253, vol. 32, No. 2.
Connell Lawrence Edwin
Miller Matthew R.
Petrie Craig S.
Ingrassia Fisher & Lorenz P.C.
Motorola Inc.
Shingleton Michael B
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