Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-04-05
2001-11-06
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S341000
Reexamination Certificate
active
06313685
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to signal processing, and more particularly to an integrator circuit that achieves offset reduction while inducing integrator leakage.
2. Description of Related Art
Today's wireless communications markets are being driven by a multitude of user benefits. Products such as cellular phones, cordless phones, pagers, and the like have freed corporate and individual users from their desks and homes and are driving the demand for additional equipment and systems to increase their utility. As a result digital radio personal communications devices will play an increasingly important role in the overall communications infrastructure in the next decade.
Mixed-signal integration and power management have taken on added importance now that analog and mixed analog-digital ICs have become the fastest-growing segment of the semiconductor industry. Integration strategies for multimedia consoles, cellular telephones and battery-powered portables are being developed, as well as applications for less integrated but highly specialized building blocks that serve multiple markets. These building blocks include data converters, comparators, demodulators, filters, amplifiers, and integrators.
One important aspect of digital radio personal communications devices is the integration of Radio Frequency (RF) sections of transceivers. Compared to other types of integrated circuits, the level of integration in the RF sections of transceivers is still relatively low. Considerations of power dissipation, low offset budgets, form factor, and cost dictate that the RF/IF portions of these devices evolve to higher levels of integration than at present. Nevertheless, there are some essential barriers to realizing these higher levels of integration.
For example, most applications provide an integrator circuit in a RF receiver system to produce a ramping of an output voltage which is linearly increasing or decreasing. For integrator circuits, low frequency amplifier noises and direct current (DC) offsets are attenuated.
A modification to a typical integrator circuit is necessary to make offset reduction practical. Generally, a capacitor used in an integrator circuit is open to DC signals. As a result, there is no negative feedback, i.e. integrator leakage, at zero frequency. Without a negative feedback, an integrator circuit interprets a DC offset voltage as a valid input voltage. The result is that the capacitor is charged, and the output voltage goes into positive or negative saturation where the output voltage stays indefinitely.
One way of reducing the effect of a DC offset in an input voltage, i.e. inducing integrator leakage, is to place a switched-capacitor in parallel to an integration capacitor, thereby removing some charge every clock cycle. However, this method would often affect the offset cancellation performance. Further, adding a switched-capacitor on chip would increase the size of a chip which is often prohibitive. Off chip switched-capacitor would increase between eight and sixteen extra pins depending on whether one or two sections of AC coupling are needed. In addition, AC coupling would have high enough corner frequency to cause settling at the beginning of a burst which produces too much DC wander for a baseband signal. As a result, a dual bandwidth AC coupling mechanism would have to be utilized.
It can be seen that there is a need for integrator leakage without placing a switched-capacitor in parallel to an integration capacitor.
It can also be seen that there is a need for an offset cancelled integrator that achieves offset reduction while also inducing integrator leak.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses an offset cancelled integrator circuit that achieves offset reduction while also inducing integrator leakage.
The present invention solves the above-described problems by providing an offset cancelled integrator circuit that induces integrator leakage while simultaneously latching and cancelling its own offset voltage via an offset capacitor (Cos).
A method in accordance with the principles of the present invention includes combining a first and second input signals to produce a charge signal, reducing the charge signal using a charge reduction signal, accumulating the reduced charge signal to generate an output signal having an offset component, wherein the output signal is used to produce the charge reduction signal. The output signal is produced via simultaneous accumulation and offset of the charged signal, wherein the offset component is reduced by leaking a fraction of the charge signal.
Other embodiments of a system in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention is that a positive component of the first input signal and a negative component of the second input signal are combined with a negative component and a positive component of the charge reduction signal, respectively, wherein the first and second input signals and the charge reduction signal accumulate on a first storage component, a second storage component, and a third storage component, respectively.
Another aspect of the present invention is that the positive component and the negative component of the input signal further includes subtracting a sum of the first and second positive components of the input signal from the negative component of the charge reduction signal, and subtracting a sum of the first and second negative components of the input signal from the positive component of the charge reduction signal.
A further aspect of the present invention is that the combination of the first and second input signals with a part of the output signal further includes modifying a positive component and a negative component of an in-phase signal and a quadrature signal.
Still another aspect of the present invention is that the accumulation further includes combining the first and second input signals with the charge reduction signal of an opposite polarity via a fourth storage component.
An additional aspect of the present invention is that the reduction of the offset component by leaking the fraction of the charge signal further includes combining the first and second input signals with the charge reduction signal of the opposite polarity via a fifth storage component.
A further another aspect of the present invention is that the accumulating of the reduced charge signal to generate the output signal further includes amplifying the positive component and the negative component of the charge signal.
Still another aspect of the present invention is that a reset signal is provided to erase a plurality of memory locations.
Still an additional aspect of the present invention is to generate a predetermined signal which produces a two-phase non-overlapping signal.
Another aspect of the present invention is that the two-phase, non-overlapping signal further produces a predetermined delayed two-phase non-overlapping signal.
Further, in one embodiment in accordance with the principles of the invention, an offset cancelled integrator circuit for integrating multiple signals includes an arithmetic circuit to combine a first and second input signals to produce a charge signal having an offset, and an offset circuit, coupled to the arithmetic circuit, to reduce the charge signal to produce a reduced charge signal. The charge signal is reduced using a charge reduction signal to leak a fraction of the charge signal and simultaneously accumulate the reduced charge signal to produce an output signal.
Another aspect of the present invention is that the arithmetic circuit includes a plurality of storage components for combining a positive component and a negative component of the input signal with a negative component and a positive component of the charge r
Level One Communications Inc.
Merchant & Gould P.C.
Tran Toan
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