Offset cancellation circuit and method of reducing pulse pairing

Details Offset cancellation circuit and method of reducing pulse pairing Offset cancellation circuit and method of reducing pulse pairing

1991-07-29

1993-01-26

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307494, 307354, 307264, 328162, 330 9, G06G 710, H03B 100

Patent

active

051824760

ABSTRACT:
An offset cancellation circuit corrects DC offset appearing at the input of a comparator circuit. The first input of a summing junction receives an input signal containing DC offset. The output of the summing junction drives the input of the comparator and a feedback amplifier, the latter of which returns to the second input of the summing junction. Any DC offset is processed through the feedback amplifier where it subtracts from the input signal for providing zero DC offset at the input of the comparator.

REFERENCES:
patent: 4377759 (1983-03-01), Ohhata et al.
patent: 4430622 (1984-02-01), Simoes
patent: 4575683 (1986-03-01), Roberts et al.
patent: 4710652 (1987-12-01), Petr
patent: 5047727 (1991-09-01), Theus

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