Offset cancellation circuit

Details Offset cancellation circuit Offset cancellation circuit

1996-05-16

1999-11-02

Gaffin, Jeffrey A.

Coded data generation or conversion

Converter compensation

327391, 327437, H03M 106

Patent

active

059778920

ABSTRACT:
An offset cancellation circuit(1) for an analog switch(10) is provided which substantially reduces the offset voltage induced by the analog switch circuit. The circuit(1) comprising a second P-channel transistor(2) and a third N-channel transistor(4) connected to each other in series, the drains of the second P-channel transistor and the third N-channel transistor being connected to the output terminal; a second N-channel transistor(3) and a third P-channel transistor(5) connected to each other in series, the drains of the second N-channel transistor and the third P-channel transistor being connected to the output terminal; the gate of the second P-channel transistor is connected to the gate of the N-channel transistor; and the gate of the second N-channel transistor is connected to the gate of the P-channel transistor.

REFERENCES:
patent: 4599522 (1986-07-01), Matsuo et al.
patent: 4651037 (1987-03-01), Ogasawara et al.
patent: 5019731 (1991-05-01), Kobayashi
patent: 5479121 (1995-12-01), Shen et al.
patent: 5517150 (1996-05-01), Okumura

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