Offset cancel latching comparator

Details Offset cancel latching comparator Offset cancel latching comparator

1989-11-17

1991-05-21

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 307494, 307497, H03K 524

Patent

active

050178059

ABSTRACT:
A differential pair of transistors (Q2, Q3), the sources of which are connected to a current source (Q1); first and second input terminals (IN, VX) connected to the gates of the first and second transistors respectively; first and second output terminals (DN, DP) connected to the drains of the second and first transistors; third and fourth transistors (Q6, Q7), the sources of which are connected to a voltage supply (UDD), the drain of the third transistor being connected to the drain of the first transistor, and the drain of the fourth transistor being connected to the drain of the second transistor; the gate of the third transistor being connected to the drain of the first transistor via first switch (Q104) and connected to the drain of the second transistor via a first capacitor (C1); and the gate of the fourth transistor being connected to the drain of the second transistor via second switch (Q5) and connected to the drain of the first transistor via a second capacitor (C2).

REFERENCES:
patent: 3849673 (1974-11-01), Koo
patent: 4802130 (1989-01-01), Soneda
patent: 4858195 (1989-08-01), Soneda

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