Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-11-04
2002-08-13
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S691000, C438S692000, C438S693000
Reexamination Certificate
active
06432823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is directed to a method and apparatus for chemical mechanical polishing, particularly in the manufacture of semiconductor wafers.
2. Description of Related Art
Fabrication of semiconductor integrated circuits (IC) is a complicated multi-step process for creating microscopic structures with various electrical properties to form a connected set of devices. As the level of integration of ICs increases, the devices become smaller and more densely packed, requiring more levels of photolithography and more processing steps. As more layers are built up on the silicon wafer, problems caused by surface non-planarity become increasingly severe and can impact yield and chip performance. During the fabrication process, it may become necessary to remove excess material in a process referred to as planarization.
Chemical mechanical polishing (CMP) is well known in the art as a planarization technique in the manufacture of semiconductor wafers. CMP involves the use of a polishing pad affixed to a circular polishing table and a holder to hold the wafer face down against the rotating pad. A slurry containing abrasive and chemical additives is dispensed onto the polishing pad. The polishing pad is typically chosen for its hardness, compressibility and ability to act as a carrier of the slurry and to wipe away the grit and debris resulting from the polishing action. As the wafer and polishing pad rotate relative to each other, the rotating action along with the abrasive and chemical additives of the slurry, result in a polishing action that removes material from the surface of the wafer. Protrusions on the surface erode more efficiently than recessed areas leading to the flattening or planarization of the wafer surface.
In conventionally designed CMP tools, the relative linear speed at the center of the carrier and thus, also at the center of the wafer, is affected by the rotation of the platen only. At other points on the wafer, particularly on the wafer edge, planarization of the wafer is affected by the rotation of both the carrier and the platen. The ability to “match” the rotations of the platen and the wafer carrier, although at different velocities, provides greater uniformity in polishing. As there are a limited number of variables to work with, it is difficult, if not impossible, to find substantial rotational optimization between the platen and the carrier.
Another disadvantage with prior art CMP tool configuration is the difficulty in achieving uniform polishing of the wafers due to the conventional distribution of slurry under the wafer during polishing. Conventional slurry delivery systems, while providing adequate amounts of slurry to the wafer edge, do not deliver enough slurry to the wafer center. Non-uniform slurry delivery is further exacerbated by the tool configuration because the wafer carrier is substantially disposed over the polishing tool. Thus, the inadequate slurry delivery results in non-uniform polishing which leads to defects on the wafer surface.
Still another disadvantage of the prior art polishing tools is the inability to provide more than one polishing application at a time. Conventional methods require that two or more polishers must be used sequentially to provide different rotational speeds of the polisher, or different textures of the polishing pads. For example, if a unique surface required polishing with polishing pads of different textures, the polishing must be performed sequentially by multiple polishing steps which is very costly and non-manufacturable. Furthermore, the necessity for multiple, sequential polishing steps require that more than one polishing tool be placed inside the clean room used during wafer manufacture taking up valuable space.
A further disadvantage of the prior art is the cumbersome in-situ methods to detect the planarization endpoint of the films on the semiconductor wafer. Since the wafer carrier is typically positioned face down over the polishing platen, it is difficult and time consuming to determine the endpoint of the film being polished without stopping the polishing process to make a determination. In-situ methods may be used which are traditionally installed inside the platen and a transparent window provided in the polishing pad. However, these in-situ methods are subject to the corrosive effects of the slurry and the quality of the detected signal is diminished since a direct measurement is not possible.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of and apparatus for planarizing semiconductor wafers or other articles in need of polishing wherein different planarization conditions may be utilized substantially simultaneously.
It is another object of the present invention to provide a method of and apparatus for matching the rotational speed of the polishing platen with the rotational speed of the wafer carrier to provide enhanced uniformity in planarization.
It is yet another object of the present invention to provide a chemical mechanical polishing tool which provides improved slurry delivery for enhanced planarization of the object being polished.
Yet another object of the present invention is to provide a method and apparatus for in-situ endpoint detection of the thickness of films being polished on a semiconductor wafer.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a tool for polishing semiconductor wafers of a pre-determined diameter comprising at least two polishing platens, the platens being positioned adjacent to each other such that polishing portions of the platens are substantially co-planar; and at least one wafer carrier moveably mounted to be positioned over the platens such that a semiconductor wafer may be polished by the platens substantially simultaneously. Preferably, each of the platens have a diameter substantially equal to the pre-determined diameter of a wafer carrier in need of polishing and wherein the at least two platens comprises three platens or wherein the at least two platens comprise four platens.
In a further aspect, the present invention is directed to a tool for polishing semiconductor wafers comprising a first polishing platen; a second polishing platen mounted adjacent to the first polishing platen, the first and second polishing platens positioned substantially co-planar too each other; and at least one wafer carrier moveably mounted adjacent the platens such that one or more semiconductor wafers mounted to the carrier may be polished by the platens substantially simultaneously. Preferably, the tool further includes a third polishing platen. Alternatively, the tool further includes both a third polishing platen and a fourth polishing platen.
The preferred embodiments of polishing tools in accordance with the present invention may further include a slurry distribution system and/or an endpoint detection system.
In a final aspect, the present invention is directed to a method of polishing a semiconductor wafer comprising the steps of: (a) providing a polishing tool comprising at least two polishing platens, the platens being positioned adjacent to each other such that polishing portions of the platens are substantially co-planar; and at least one wafer carrier movably mounted adjacent the platens such that one or more semiconductor wafers mounted to the carrier may be polished by the at least two platens substantially simultaneously; (b) providing at least one semiconductor wafer in need of polishing; (c) contacting the semiconductor wafer to the polishing platens; (d) polishing the semiconductor wafer; and (e) removing a desired thickness of the semiconductor wafer.
REFERENCES:
patent: 4587768 (1986-05-01), Doyle
patent: 5187901 (1993-02-01), K
Huynh Cuc K.
Manfredi Paul A.
Martin Thomas J.
Nadeau Douglas P.
Wu Yutong
DeLio & Peterson LLC
International Business Machines - Corporation
R. Vanessa
Tomaszewski John J.
Utech Benjamin L.
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