Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Calibration
Reexamination Certificate
1999-06-09
2001-08-28
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Calibration
C324S719000
Reexamination Certificate
active
06281687
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to digital output drivers for CMOS integrated circuits. More particularly, it relates to a circuit for calibrating the drive impedances of a group of CMOS output drivers.
BACKGROUND OF THE INVENTION
Dynamically calibrating the impedance of an output driver on an integrated circuit can have several advantages. It can reduce reflections on the output signal, reduce electromagnetic interference (EMI), reduce power dissipation, and reduce signal skew.
On a CMOS integrated circuit (IC), one way of controlling the impedance of an output driver is to split the pull-up transistor (typically a p-channel MOSFET (PFET) with it's source connected to the positive supply, VDD) and the pull-down transistor (typically a n-channel MOSFET (NFET) with it's source connected to the negative supply, GND) into multiple transistors. When the output driver is driving, each of these multiple transistors is then appropriately controlled to turn on, or remain off, according to a set of calibration signals such that the desired output impedance is achieved. Since the pull-up and pull-down transistors typically have different conductance and are sized differently, they usually require different sets of calibration signals. Normally, to generate these two set of calibration signals, two external resistors are used (one for the pull-up FETs and one for the pull-down FETs). This uses two calibration pins for each section of the chip that requires a different drive impedance. Since prudence would suggest having differently calibrated drivers for each side of the chip to compensate for process, voltage, and temperature fluctuations across a die as well as a different impedance for each type of signal, or group of signals, a large number of pins may have to be used as calibration pins. This increases the cost of the chip, and the assembly cost of any board the chip is used on.
Accordingly there is a need in the art for a way to reduce the number of pins and external resistors required for an impedance controlled CMOS output driver.
SUMMARY OF THE INVENTION
A preferred embodiment of the invention provides multiple sets of calibration signals but only uses two calibration pins and one external resistor. The invention may be implemented using standard CMOS circuits and may be used with existing controlled impedance output driver circuits.
An embodiment of the invention multiplexes the use of a single external calibration resistor between the calibration circuitry for multiple signal groups as well as the pull-up and pull-down calibration circuitry within signals groups. The calibration circuitry for a particular group and transistor type is assigned a time slice that it can use the calibration resistor. This ensures that only one of the calibration circuits is updating at a time. The other calibration circuits are controlled to hold their value. The drive transistors of the calibration circuits may be controlled to be either all on, or all off, depending on whether they match the type of transistor being calibrated.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 3628059 (1971-12-01), Niu
patent: 3675484 (1972-07-01), Pederson
patent: 3875427 (1975-04-01), Riley
patent: 3879668 (1975-04-01), Edwards
patent: 3880006 (1975-04-01), Poduje
patent: 3940752 (1976-02-01), Bair
patent: 3986109 (1976-10-01), Poduje
patent: 4001675 (1977-01-01), Veleber
patent: 4081744 (1978-03-01), Ray
patent: 4158863 (1979-06-01), Naylor
patent: 4331913 (1982-05-01), Sparber
patent: 4623799 (1986-11-01), Nyman, Jr.
patent: 4801895 (1989-01-01), Melandri
patent: 4843306 (1989-06-01), Meuller
patent: 4922130 (1990-05-01), Swerlein
patent: 4935645 (1990-06-01), Lee
patent: 4951236 (1990-08-01), Kawate et al.
patent: 4982164 (1991-01-01), Schiek et al.
patent: 5088325 (1992-02-01), Eichberger et al.
patent: 5245873 (1993-09-01), Fathauer et al.
patent: 5402082 (1995-03-01), Eccleston et al.
patent: 5442296 (1995-08-01), Schiek et al.
patent: 5481199 (1996-01-01), Anderson et al.
patent: 5532983 (1996-07-01), Madrid et al.
patent: 5548288 (1996-08-01), Lueng
patent: 5621310 (1997-04-01), Cosgrove et al.
patent: 5717321 (1998-02-01), Kerth et al.
patent: 5886529 (1999-03-01), Wakamatsu
patent: 6046632 (1998-09-01), Straw
Agilent Technologies
Brown Glenn W.
Hamdan Wasseem H.
Neudeck Alexander J.
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