Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2001-11-02
2004-10-12
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S784000, C257S786000, C438S617000, C228S180500
Reexamination Certificate
active
06803665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally in the field of semiconductor chip fabrication. More specifically, the present invention is in the field of inductors for semiconductor chips.
2. Background Art
The requirement of smaller, more complex, and faster devices operating at high frequencies, such as wireless communications devices and Bluetooth RF transceivers, has also resulted in an increased demand for small size inductors. These small wireless communication devices and Bluetooth RF transceivers contain semiconductor chip packages and semiconductor dies with power and low noise amplifiers that require small size, high quality factor (“Q”) inductors for use in the resonance and matching circuits. Various approaches are currently used for adding small size inductors to semiconductor chip packages and semiconductor dies. However, each of the current approaches has various undesirable side effects associated with it.
One approach for adding small size inductors involves designing inductors into the semiconductor die itself. However, when designing an inductor into the semiconductor die, the amount of area required for the inductor increases the size of the semiconductor die and additional processing of the wafer during fabrication might also be required. Both increasing the size of the semiconductor die and additional processing of the wafer increase the cost and also adversely impacts the yield of the semiconductor die.
One approach for adding small size inductors includes surface mounting discrete inductors onto the package substrate. However, in order to surface mount discrete inductors onto the package substrate, several additional process steps are required. These additional steps in the assembly process, such as surface mounting of the discrete inductors, increases the overall cost of the assembly, and may also reduce the assembly yield. Further, surface mounting discrete inductors onto the package substrate increases the overall size of the assembly.
Yet another approach adds small size inductors to the semiconductor chip package by designing printed inductors onto the semiconductor chip package. However, once the printed inductor has been defined on the package substrate, the inductance of the printed inductor cannot be altered without redesigning the package substrate. Thus, the exact value of the printed inductor must match the predetermined simulated value of inductance required in a particular circuit. One option to alleviate this problem is to trim the inductor by laser after the semiconductor die package has been assembled. Although this option allows the inductance of printed inductor to be adjusted to meet a required value, the above option is costly and difficult to implement.
Thus, there exists a need in the art for structure and method for fabricating an inductor on the surface of a semiconductor die that has a high “Q” and is small in size. Moreover, there exists a need in the art for a structure and method for fabricating an inductor on the surface of a semiconductor die that allows the inductance of the inductor to be easily adjusted to meet a specific design requirement. Further, there exists a need in the art for structure and method for fabricating an inductor on the surface of a semiconductor die that is cost effective and does not increase the size of the semiconductor die.
SUMMARY OF THE INVENTION
The present invention is directed to an off-chip inductor. The various embodiments of the present invention result in a small size and high quality factor inductor on a semiconductor die. Moreover, the present invention allows the inductance of the inductor to be easily adjusted to meet a specific design requirement. Further, the invention is cost effective and does not increase the size of the semiconductor die.
According to an embodiment of the present invention, a semiconductor die has a source bond pad and a destination bond pad attached to a top surface of the semiconductor die. A stud bump is situated on the destination bond pad. In one embodiment, the stud bump is fabricated by first forming a ball bond and then cutting the bonding wire above the bonding point, leaving a stud of bonding wire material on the destination bond pad. A bonding wire is then ball bonded to the source bond pad and thereafter stitch bonded to the stud bump on the destination bond pad. The bonding wire acts as an off-chip inductor or a portion of an off-chip inductor.
In one embodiment a number of bonding wires and on chip conductors are used to form an off-chip inductor. In all embodiments of the present invention, the inductance of the off-chip inductor can be adjusted or fine-tuned by adjusting a loop height of the one or more bonding wires used in the off-chip inductor. The inductance of the invention's off-chip inductor can also be adjusted by increasing or decreasing the number of bonding wires used to form the off-chip inductor. Various other details and advantages of the present invention are explained in the following detailed description.
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Cote Kevin J.
Hashemi Hassan S.
Megahed Mohamed A.
Chambliss Alonzo
Farjami & Farjami LLP
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