Boots – shoes – and leggings
Patent
1993-12-23
1994-12-06
Bowler, Alyssa H.
Boots, shoes, and leggings
395575, 395375, 364DIG2, 364941, 364DIG1, 3642674, G06F 1100
Patent
active
053718941
ABSTRACT:
The invention is a system and method for providing a breakpoint exception at any predetermined instruction address in a processor system of the type including an integrated circuit microprocessor and an instruction cache and memory management unit (CMMU) where code addresses are sent to the instruction CMMU and the instruction CMMU returns with code instructions and returns with a FAULT code reply signal when there is no reply code, and wherein an exception is forced in the microprocessor in response to the FAULT code reply signal. The system comprises at least one breakpoint register for storing a predetermined breakpoint address, a means for comparing the code addresses which are sent to the CMMU with the predetermined breakpoint address in the breakpoint register and for generating a match signal when equivalent addresses are detected, and a means coupled to the CMMU and responsive to said match signal for causing said CMMU to issue a FAULT code reply signal, whereby an exception is forced in the microprocessor. The system is especially suitable for use with the Motorola MC88100 processor and MC88200 CMMU.
REFERENCES:
patent: 3937938 (1976-02-01), Matthews
patent: 4080650 (1978-03-01), Beckett
patent: 4338660 (1982-07-01), Kelley et al.
patent: 4429368 (1984-01-01), Kurii
patent: 4635193 (1987-01-01), Moyer et al.
patent: 4675646 (1987-06-01), Lauer
patent: 4742452 (1988-05-01), Hirokawa
patent: 4813009 (1989-03-01), Tallman
patent: 4819234 (1989-04-01), Huber
patent: 4860195 (1989-08-01), Krauskopf
patent: 4866665 (1989-09-01), Haswell-Smith
patent: 4879646 (1989-11-01), Iwasaki et al.
patent: 4942524 (1990-07-01), Nunomura
patent: 4954942 (1990-09-01), Masuda et al.
patent: 4972388 (1990-11-01), Crawford et al.
patent: 5053944 (1991-10-01), Krauskopf
patent: 5113572 (1992-05-01), Dinwiddie
patent: 5165027 (1992-11-01), Krauskopf
patent: 5173872 (1992-12-01), Crawford et al.
MC 88110 Second Generation RISC Microprocesser User's Manual; 1991.
Wilson; "As RISC Wars Escalate, Simplicity Seems to be First Casualty" Computer Design; Dec. 1, 1990.
"Motorola reveals 88000 strategy: 88110 previewed--88300 embedded strategy outlined: Microprocessor Report", Nov. 7, 1990.
MC88200 Cache/Memory Management Unit User's Manual, 1988, pp. 2.24-2.34, 7.1-7.5.
Alsup, "Motorola's 88000 Family Architecture" Jun. 1990, IEEE Micro.
"Motorola expands 88000 MPU line" Oct. 1990, Electronic News, Summary only "Data General Claims to Lead With Four-CPU Avion", Mar. 1991; Computergram International.
MC88100 RISC Microprocessor User Manual 1988, p. 8-3.
Bowler Alyssa H.
Donaghue L.
International Business Machines - Corporation
LandOfFree
Off-chip breakpoint system for a pipelined microprocessor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Off-chip breakpoint system for a pipelined microprocessor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Off-chip breakpoint system for a pipelined microprocessor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-222482