Off-chip access for psuedo-microprogramming in microprocessor

Details Off-chip access for psuedo-microprogramming in microprocessor Off-chip access for psuedo-microprogramming in microprocessor

1980-11-24

1984-02-28

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 930, G06F 1306

Patent

active

044344627

ABSTRACT:
A single-chip microprocessor device of the MOS/LSI type contains an ALU, internal busses, address/data registers, an instruction register, and control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by control lines and a bidirectional multiplexed address/data bus. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM not in the main off-chip memory map) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. Also, off-chip access of another memory separate from the main memory allows emulator functions or special instructions.

REFERENCES:
patent: 3757306 (1973-09-01), Boone
patent: 4086626 (1978-04-01), Chung
patent: 4087854 (1978-05-01), Kinoshita et al.
patent: 4093982 (1978-06-01), Heuer et al.

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