Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
1999-10-20
2001-06-19
Banks, Derris H. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S028000
Reexamination Certificate
active
06248002
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of semiconductor devices, and more specifically to a method of removing accumulated slurry during the polishing of a semiconductor surface that contains W plug.
(2) Description of the Prior Art
During the fabrication of VLSI and ULSI semiconductor wafers, it is critically important to use wafers that are free of any surface particles or impurities since the presence of these impurities has a direct and negative effect on device yield and throughput. It is therefore of extreme importance to use effective means for the control and removal of these impurities from the surface of the wafer since these impurities may, during further high temperature processing steps, diffuse into the wafer surface thereby substantially altering the chemical composition of the wafer. In addition, impurities can be classified as donor or acceptor dopants, these dopants will have an impact on the performance of subsequently produced semiconductor devices. Yet other impurities may cause surface dislocations or internal stacking misalignments or faults further having a negative impact on semiconductor manufacturing yield and cost. It is therefore clear that an effective method must be available to thoroughly clean the surface of the semiconductor substrate from all impurities while this process of removal may have to be repeated at various intervals during the complete processing sequence.
The first processing step during wafer processing typically is a step of cleaning the wafer surface in order to remove all loose impurities. These impurities may have been introduced by atmospheric contaminants or semiconductor or chemical particles or residue left over and contained within the processing equipment from prior usage of this equipment.
After this first step of cleaning is completed, the wafer surface typically is treated with organic compounds to remove organic impurities such as greases or hydrocarbons. Typical organic compounds used for this step are acetone, trichloroethylene, methanol and ethanol.
As a final step in the cleaning process inorganic chemicals are used. These inorganic chemical mixtures are strong oxidants that form a thin oxide layer on the surface of the semiconductor wafer. As part of this process, this oxide layer is removed thereby removing the impurities that have been absorbed into the oxide layer.
The Chemical Mechanical Polishing process uses commercially available cleaning systems. These cleaning systems use a combination of rotating pads each pad being in direct physical contact with the wafer surface and, due to the rotating movement of the polishing pad with respect to the wafer surface, planarizes by means of an abrasive action, the top surface of the semiconductor wafer. The turntables used for this purpose typically rotate at various controlled speeds, for instance 10 to 100 RPM, in a controlled clockwise or counterclockwise direction. The wafer is clamped and held, typically face downward, against the rotating polishing pad. The size of the diameter of the polishing pads is typically considerably larger than the size of the diameter of the semiconductor substrate. This means that more than one polishing pad can be arranged to simultaneously polish the surface of the wafer, these polishing pads typically being arranged in circular patterns around the center of the wafer that is being polished.
Polishing pads are typically fabricated from a polyurethane and/or polyester base material and are commercially available such as models IC1000 or Scuba IV of a woven polyurethane material.
Chemical Mechanical Polishing (CMP) is a method of polishing materials, such as semiconductor substrates, to a high degree of planarity and uniformity. The process is used to planarize semiconductor slices prior to the fabrication of semiconductor circuitry thereon, and is also used to remove high elevation features created during the fabrication of the microelectronic circuitry on the substrate. One typical chemical mechanical polishing process uses a large polishing pad that is located on a rotating platen against which a substrate is positioned for polishing, and a positioning member which positions and biases the substrate on the rotating polishing pad. Chemical slurry, which may also include abrasive materials therein, is maintained on the polishing pad to modify the polishing characteristics of the polishing pad in order to enhance the polishing of the substrate.
One factor, which contributes to the unpredictability and non-uniformity of the polishing rate of the CMP process, is the non-homogeneous replenishment of slurry at the surface of the substrate and the polishing pad. The slurry is primarily used to enhance the rate at which selected materials are removed from the substrate surface. As a fixed volume of slurry in contact with the substrate reacts with the selected materials on the surface of the substrate, this fixed volume of slurry becomes less reactive and the polishing enhancing characteristics of that fixed volume of slurry is significantly reduced. One approach to overcoming this problem is to continuously provide fresh slurry onto the polishing pad.
In the CMP process, semiconductor substrates are rotated, face down, against a polishing pad in the presence of abrasive slurry. Most commonly, the layer to be planarized is an electrical insulating layer overlaying active circuit devices. As the substrate is rotated against the polishing pad, the abrasive force grinds away the surface of the insulating layer. Additionally, chemical compounds within the slurry undergo a chemical reaction with the components of the insulating layer to enhance the rate of removal. By carefully selecting the chemical components of the slurry, the polishing process can be made more selective to one type of material than to another. For example, in the presence of potassium hydroxide, silicon dioxide is removed at a faster rate than silicon nitride. The ability to control the selectivity of a CMP process has led to increased use in the fabrication of complex integrated circuits.
Specifically, applying the CMP process to Intra Level Dielectric (ILD) and Inter Metal Dielectric (IMD) that are used for the manufacturing of semiconductor wafers, surface imperfections (micro-scratch) typically present a problem. Imperfections caused by micro-scratches in the ILD and IMD can range from 100 to 1000 EA for 200 mm. wafers, where an imperfection typically has a depth from 500 to 900 A
0
and a width of from 1000 to 3000 A
0
. As part of the polishing process of the ILD and IMD, a tungsten film is deposited; the surface imperfections will be filled with tungsten during this deposition. For devices within the semiconductor wafer with a dimension of 0.35 um. or larger, an etching process is used where the tungsten that has entered the imperfections within the wafer surface can be removed. For the larger size devices within the semiconductor wafer there is therefore no negative impact on the yield of these devices. For device sizes within the semiconductor wafer of 0.25 um or less, the indicated procedure of etching the tungsten layer is no longer effective. This results in relative large imperfections within the surface of the wafer, large with respect to the size of the semiconductor devices. These imperfections will cause shorts between the metal lines within the devices while the imperfections also have a severe negative impact on device yield and device reliability.
As part of the CMP process, oxide slurry can also be used. A typical CMP process uses only one polishing pad, this pad being a hard polishing pad, for instance an IC 1000 pad. In polishing a semiconductor surface wherein wolfram plugs have been created as part of the damascene process, it is found that the plug protrudes from the semiconductor surface be about 1000 Angstrom. This protrusion will have an impact on the polishing process since the plug protrusion interrupts the constant and uniform contact between the polishing pad and the surface of the se
Kuan Tong-Hua
Lin Yu-Ku
Wang Hui-Ling
Wang Ying-Lang
Ackerman Stephen B.
Banks Derris H.
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Obtaining the better defect performance of the fuse CMP... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Obtaining the better defect performance of the fuse CMP..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Obtaining the better defect performance of the fuse CMP... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2469122