Object placement aid

Details Object placement aid Object placement aid

1994-06-03

1996-07-09

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 395921, G06F 1750

Patent

active

055351344

ABSTRACT:
An existing layout is modified to ensure compliance with design rules and any user-defined rules by deriving a horizontal constraint model and a vertical constraint model. For each of the vertical and horizontal orientations in turn, violations of the rules are identified. For each orientation in turn, the violations are removed in such a way that objects in the layout are moved the least amount necessary. A given object may also be inserted into an existing layout in such a way that perturbation of objects in the existing layout is minimized by exploring solutions allowing for object merger and non-merger solutions and choosing the best one based on predetermined criteria. Given a group of objects, a layout may also be created in such a way that successive objects are placed to minimize movement of objects already placed. Placement of an object in an existing layout may also be improved by removing the object and inserting it as if it were a new object a number of times until no further improvement is noted in its placement.

REFERENCES:
patent: 3617714 (1971-11-01), Kernigham et al.
patent: 3654615 (1972-04-01), Freitag
patent: 4551810 (1985-11-01), Levine
patent: 4554625 (1985-11-01), Otten
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4630219 (1986-12-01), Di Giacomo et al.
patent: 4639604 (1987-01-01), Murakami et al.
patent: 4686629 (1987-08-01), Noto et al.
patent: 4754408 (1988-06-01), Carpenter et al.
patent: 4805113 (1989-02-01), Ishii et al.
patent: 4812962 (1989-03-01), Witt
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 4908772 (1990-03-01), Chi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 5140402 (1992-08-01), Murakata
patent: 5144563 (1992-09-01), Date et al.
patent: 5164907 (1992-11-01), Yabe
patent: 5175696 (1992-12-01), Hooper et al.
patent: 5191542 (1993-03-01), Murofushi
patent: 5200908 (1993-04-01), Date et al.
patent: 5218551 (1993-06-01), Agrawal
patent: 5222031 (1993-06-01), Kaida
patent: 5224056 (1993-06-01), Chene et al.
patent: 5225991 (1993-07-01), Dougherty
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5267176 (1993-11-01), Antreich et al.
patent: 5281558 (1994-01-01), Bamji et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5308798 (1994-05-01), Brasen et al.
patent: 5311443 (1994-05-01), Crain et al.
patent: 5359538 (1994-10-01), Hui et al.
patent: 5363313 (1994-11-01), Lee
patent: 5416722 (1995-05-01), Edwards
patent: 5420800 (1995-05-01), Fukui
patent: 5430831 (1995-07-01), Snellen
patent: 5465218 (1995-11-01), Handa
patent: 5475608 (1995-12-01), Masuoka
Tsay, R-S et al., "Proud: A Sea-Of-Gates Placement Algorithm", IEEE Design & Test of Computers, pp. 44-56, 1988.
Polak, S. D. and Tsay, R-S, "A Combined Deterministic and Random Optimization Algorithm for the Placement of Macro-Cells", Department of Electrical Engineering and Computer Sciences, University of California, Berkeley.
Flemming, U., "Wall Representations of Rectangular Dissections an Their Use in Automated Space Allocation", Environment and Planning B., vol. 5, pp., 215-232, 1978.
Flemming, U., "More on the Representation and Generation of Loosely Packed Arrangements of Rectangles", Environment and Planning B: Planning and Design, vol. 16, pp. 327-359, 1989.
Charbon, E., et al., "A Constraint-Driven Placement Methodology for Analog Itegrated Circuits", IEEE 1992 Custom Integrated Circuits Conference, pp. 28.2.1-28.2.4, 1992.
Rijmenants, J. et al., "ILAC: An Automated Layout Tool for Analog CMOS Circuits", IEEE 1988 Custom Integrated Circuits Conference, pp. 7.6.1-7.6.4, 9188.
Rjimenants, J., et al., "ILAC: An Automated Layout Tool for Analog CMOS Circuits", IEEE Journal of Solid-State Circuits, vol. 24, No. 2, pp. 417-425, Apr. 1989.
Cohn, John, et al., "KOAN/Anagram II: New Tools for Device-Level Analog Placement and Routing", IEEE Journal of Solid-State Circuits, vol.26, No. 3, pp. 330-342, Mar. 1991.
Bar-Yehuda, R., et al., "Depth-First-Search and Dynamic Programming Algorithms for Efficient CMOS Cell Generation", IEEE Transactions on Computer-Aided Design, vol. 8, No. 7, pp. 737-743, Jul., 1989.
Uehara, T., and Van Cleemput, W., "Optimal Layout of CMOS Functional Arrays", IEEE Transactions on Computers, vol. c-30, No. 5, pp. 305-32, 1981.
Scott, W. S. and Ousterhout, J. K., "Plowing: Interactive Stretching and Compaction in Magic", IEEE 21st Design Automation Conference, Paper 11.3, pp. 66-172, 1984.
Ousterhout, J. K., Hamachi, G. T. and Mayo, R. N., "Magic: A VLSI Layout System", IEEE 21st Design Automation Conference, Paper 11.1, pp. 152-159, 1984.

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