Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-03-16
2002-07-02
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185030, C365S185050, C365S185280, C365S154000
Reexamination Certificate
active
06414873
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile, static random access memory (nvSRAM).
BACKGROUND OF THE INVENTION
In general, a computer system is comprised of a memory for holding data and programs, a processor for executing the programs or operating on the data held in memory, and an input/output device for facilitating communications between the computer system and a user. There are several different types of digital memories available for use in the memory portion of a computer system. In many instances, the particular application in which the computer system is intended to be used dictates the type of memory that is appropriate for all or a portion of the memory of the computer system. For instance, one application for a computer system in which an nvSRAM may be appropriate is in a portable. computer system. Portable computer systems are generally designed to operate, if needed, with power supplied by a battery housed within the system. If the battery becomes incapable of providing power to the system and an alternative source of power is not available, the data held in memory could become irretrievably lost. In such applications, it is desirable to use an nvSRAM because the static random, access memory (SRAM) portion is capable of retaining the data while power is present and providing the performance needed during normal operations, and the non-volatile memory (nv) portion is capable of retaining data for an extended period of time after power has been removed and once power is restored, re-establishing the data in the SRAM portion.
A basic nvSRAM memory device is comprised of: (1) a plurality of nvSRAM memory cells; and (2) a controller for managing the operations of the nvSRAM memory cells. A typical nvSRAM cell is comprised of a static random access memory cell and a non-volatile memory cell. Briefly, the terms “random access memory” and “RAM” refer to the ability to access any one of a plurality of cells in the memory at any time to write/read data to/from the accessed cell. In contrast, other types of memory require that other memory locations be traversed before the desired memory location can be accessed. These types of memories (magnetic tape, for example) are typically much slower than a random access memories. The term “static” refers to the ability of the memory to retain data as long as power is being supplied. In contrast, the term “dynamic” refers to memories that retain data as long as power is being supplied and the memory is being periodically refreshed. The term non-volatile refers to the ability of a memory cell to retain data in the absence of power.
The SRAM memory cell in an nvSRAM cell is capable of communicating a bit of data to and from an exterior environment. Additionally, the SRAM memory cell can provide the nv memory cell with a copy of the bit of data, thereby providing backup storage to the SRAM cell in the event power is removed from the nvSRAM cell. The SRAM cell, as long as power is being provided, is capable of: (1) receiving a bit of data from an exterior environment; (2) retaining the bit of data; and (3) transmitting the bit of data back to the exterior environment. If, however, power is removed from the SRAM memory cell, the SRAM memory cell will lose the bit of data. The nv cell prevents such a loss by providing a backup to the SRAM memory cell. In backing up the SRAM memory cell, the nv memory cell provides the ability to: (1) receive a copy of the bit of data stored in the SRAM memory cell; (2) retain the bit of data in the absence of power being provided to the nvSRAM memory cell; and (3) return the bit of data to the SRAM cell when power is present. The copying of a bit of data from the SRAM memory cell into the nv memory cell is referred to as a store operation. The store operation has two phases, an erase phase and a program phase. In the erase phase, the nv memory cell is conditioned so that it can accept a copy of the bit of data presently retained in the SRAM memory cell. The program phase involves copying the bit of data in the SRAM memory cell to the nv memory cell. Returning a previously copied bit of data from the nv memory cell to the SRAM memory cell is referred to as a recall operation.
SUMMARY OF THE INVENTION
The present invention provides an nvSRAM that, for every SRAM memory cell, has an nv portion that is comprised of a plurality of nv memory cells. By providing a plurality of nv memory cells, a plurality of data bits existing in the SRAM memory cell at different times can be stored in the nv portion and then later recalled to the SRAM portion. For example, in an array of nvSRAMs in which two nv memory cells are associated with each SRAM memory cell, the first nv memory cell associated with each SRAM memory cell could store information relating to a first picture that is to be displayed on the monitor of a computer system and the second nv memory cell associated with each SRAM memory cell could store information relating to a second picture that is also to be displayed on the monitor. An nvSRAM with more. than two nv memory cells for each SRAM is also possible.
In one embodiment, the nvSRAM provides the flexibility of allowing the nv memory cells to be randomly programmed, i.e., programmed in any order. For example, in an nvSRAM in which two, series-connected, nv memory cells are associated with each SRAM memory cell and the first nv memory cell is located closer to the SRAM memory cell than the second nv memory cell, the controller is capable of causing the first nv memory cell to be programmed before the second memory cell and visa versa. In one embodiment, this flexibility is achieved by implementing an nvSRAM structure that, with respect to each of the nv memory cells associated with a specific SRAM, causes one of two transistors that form an nv memory cell to be programmed and the other transistor to be dynamically program inhibited during a store operation. The ability to perform a dynamic program inhibit has the advantages of: (1) allowing random programming of the series-connected nv memory cells; (2) reducing the number of nodes within the nvSRAM to which high voltage must be applied; and (3) allowing the spacing between circuit elements to be reduced, thereby permitting a greater density of nvSRAMS cells for a given area.
In a further embodiment, the nvSRAM includes a controller for issuing the signals that permit the bits of data stored in the nv memory cells to be randomly recalled into the SRAM memory cell. For example, in an nvSRAM in which two, series-connected nv memory cells are associated with each SRAM memory cell and the first nv memory cell is located closer to the SRAM memory cell than the second nv memory cell, the controller is capable of causing the bit of data stored in the second nv memory cell to be recalled before the bit of data in the first memory cell and visa versa.
As previously noted, one type of nvSRAM associates at least two, series-connect nv memory cells with an SRAM cell. Another embodiment, however, employs at least two, parallel-connected nv memory cells with an SRAM cell.
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Ho Hoai V.
Holme Roberts & Owen LLP
Kulish, Esq. Christopher J.
Simtek Corporation
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