Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2006-09-26
2006-09-26
Nguyen, Tuan T. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185280, C365S185190, C365S185290
Reexamination Certificate
active
07113427
ABSTRACT:
NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5754475 (1998-05-01), Bill et al.
patent: 5991517 (1999-11-01), Harari et al.
patent: 6137723 (2000-10-01), Bergemont et al.
patent: 6373747 (2002-04-01), Harari et al.
patent: 6788572 (2004-09-01), Yamada et al.
U.S. Appl. No. 10/895,710, filed Jul. 8, 2004.
U.S. Appl. No. 10/895,711, filed Jul. 8, 2004.
U.S. Appl. No. 10/895,713, filed Jul. 8, 2004.
U.S. Appl. No. 10/895,712, filed Jul. 8, 2004.
U.S. Appl. No. 11/057,355, filed Feb. 14, 2005.
“Everything a System Engineer Needs to Know About Serial EEPROM Endurance”, http://ww1.microchip.com/downloads/en/AppNotes/00537.pdf, © 1992 Microchip Technology Inc., 10 Pages.
Lorenzini, M. et al., “A dual gate flash EEPROM cell with two-bits storage capacity”, Nonvolatile Memory Technology Conference, 1996., Sixth Biennial IEEE International, Publication Date: Jun. 24-26, 1996, pp. 84-90 Albuquerque, NM, USA, ISBN: 0-7803-3510-4.
Hopper Peter J.
Lindorfer Philipp
Mirgorodski Yuri
Vashchenko Vladislav
Beyer Weaver & Thomas LLP
National Semiconductor Corporation
Nguyen Tuan T.
LandOfFree
NVM PMOS-cell with one erased and two programmed states does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with NVM PMOS-cell with one erased and two programmed states, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and NVM PMOS-cell with one erased and two programmed states will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3593249