Numerical control system using a personal computer and a method

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39520039, G05B 534

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active

058503382

ABSTRACT:
A PLL circuit 31 of a pulse convert/output circuit 12 in an NC board A 1 receives a fundamental clock signal CLK through a PC extension bus 207 from a fundamental clock generating circuit 201, and generates a sync pulse signal PLS on the basis of the received fundamental clock signal CLK. The sync pulse signal PLS is inputted to a gate 34. A signal select circuit 33 receives an address signal AD, or a RESET signal or an IRQ signal through the PC extension bus 207, and generates a pulse-outputting permission signal N3 on the basis of the received signal. The pulse-outputting permission signal N3 controls a gate 34 which determines the timing of starting the outputting of the sync pulse signal PLS. Consequently, a sync signal PLSOUT that is synchronized with those in the remaining NC boards is generated.

REFERENCES:
patent: 4228495 (1980-10-01), Bernhard et al.
patent: 4263647 (1981-04-01), Merrell et al.
patent: 4618953 (1986-10-01), Daniels et al.
patent: 4635186 (1987-01-01), Oman et al.

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