Boots – shoes – and leggings
Patent
1994-07-11
1997-08-19
Mai, Tan V.
Boots, shoes, and leggings
3647462, G06F 738
Patent
active
056594950
ABSTRACT:
A numeric processor includes a multiply-add circuit with redundant value interface circuitry for performing mathematical function computations as a succession of product sums using redundant binary format values (such as signed digit) as the multiplicand and/or the addend inputs to the multiply-add circuit. The redundant value interface circuitry (i) extracts a predetermined number of bits from a redundant product sum to form a redundant truncated product sum, and (ii) couples the redundant truncated product sum to either, or both, multiplicand and addend inputs. In this manner, successive redundant product sums are calculated using without conversion to nonredundant binary format. In a preferred embodiment, the numeric processor includes a single multiply-add circuit, with redundant truncated product sum values being fed back to the multiplicand and/or addend inputs.
REFERENCES:
patent: 3591787 (1971-07-01), Freiman
patent: 4337519 (1982-06-01), Nishimoto
patent: 4594678 (1986-06-01), Uhlenhoff
patent: 4868777 (1989-09-01), Nishiyama et al.
patent: 4878190 (1989-10-01), Darley et al.
patent: 5289398 (1994-02-01), Miyoshi et al.
Briggs Willard Stuart
Matula David William
Cyrix Corporation
Mai Tan V.
Maxin John L.
Viger Andrew S.
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