Null convention adder

Details Null convention adder Null convention adder

1995-06-07

1998-08-11

Elmore, Reba I.

Boots, shoes, and leggings

364784, 395800, G06F 750

Patent

active

057936625

ABSTRACT:
A NULL convention full adder receives a plurality of inputs, each having an asserted state and a NULL state. The adder switches its output to an asserted state when all inputs have been received and summed. The adder switches its output to the NULL state only after all inputs have returned to NULL. A register can be incorporated into each full adder. Multiple full adders are combined into multi-bit adders with registration.

REFERENCES:
patent: 4140920 (1979-02-01), Dao et al.
patent: 4845633 (1989-07-01), Furtek
Daniel Hampel and Robert Winder, Threshold Logic, IEEE Spectrum, May 1971, pp. 32-39.
M.R. Greenstreet, T.E. Williams, and J. Staunstrup, Self-Timed Iteration, Elsevier Science Publishers B.V. (North-Holland), IFIP, 1988, pp. 309-322.
Teresa H.-Y. Meng, Robert W. Broderson, and David G. Messerschmitt, Automatic Synthesis of Asynchronous Circuits from High-Level Specifications, IEEE Transactions on Computer-Aided Design, vol. 8, No. 11, Nov. 1989, pp. 1185-1205.
Ted Williams, Latency and Throughput Tradeoffs in Self-Timed Speed-Independent Pipelines and Rings, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
Jens Sparso and Jorgen Staunstrup, Delay-insensitive multi-ring structures, Integration, the VLSI Journal 15, 1993, Elsevier Science Publishers B.V., pp. 313-340.
Tzyh-Yung Wuu and Sarma B.K. Vrudhula, A Design of a Fast and Area Efficient Multi-Input Muller C-element, IEEE Transactions on VLSI Systems, vol. 1, No. 2, Jun. 1993, pp. 215-219.
Marc Renaudin and Bachar El Hassan, The Design of Fast Asynchronous Adder Structures and Their Implementation Using D.C.V.S. Logic, Int'l. Symposium on Circuits & Systems, vol. 4, 1994, pp. 291-294.
Richard G. Buford, Xingcha Fan and Neil W. Bergmann, An 180 Mhz 16 bit Multiplier Using Asynchronous Logic Design Techniques, IEEE 1994 Custom Integrated Circuits Conference, pp. 215-218.
Ted Williams, Self-Timed Rings and Their Application to Division, Stanford University Technical Report No. CSL-TR-91-482, May 1991.
David E. Muller, Asynchronous Logics and Applications to Information Processing, Stanford University Press, Switching Theory In Space Technology, pp. 289-297, 1963.
Narinder Pal Singh, A Design Methodology For Self-Timed Systems, Massachusetts Institute of Technology, MIT/LCS/TR-258, Feb. 1981.
T.S. Anatharaman, A Delay Insensitive Regular Expression Recognizer, Dept. of Computer Science, Carnegie-Mellon University, CMU-CS-89-109, Jan. 1989.
Jens Sparso, et al., Design of Delay Insensitive Circuits Using Multi-Ring Structures, European Design Automation Conference, IEEE 0-8186-2780, pp. 15-20, Aug. 1992.
Lawrence G. Heller, et al., Cascode Voltage Switch Logic: A Different CMOS Logic Family, ISSCC 84 Digest of Technical Papers, IEEE, pp. 16-17, Feb. 1984.
Stephen H. Unger, Asynchronous Sequential Switching Circuits, 1969, pp. 221-229.
Carver Mead & Lynn Conway, Introduction to VLSI Systems, 1980, pp. 242-262.
Ivan E. Sutherland, Micropipelines, Communications of the ACM, Dec. 1989, vol. 32, No. 6.
Tadashi Shibata & Tadahiro Ohmi, A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations, IEEE Transactions On Electron Devices, Dec. 1992, vol. 39, No. 6, pp. 1444-1455.
Anthony S. Wojcik & Kwang-Ya Fang, On The Design Of Three-Valued Asynchronous Modules, IEEE Transactions On Computers, Oct. 1990, vol. c-29, No. 10, pp. 889-898.
Mark Edmund Dean, Strip: A Self-Time Risc Processor, Stanford University Computer Systems Laboratory Technical Report No. CSL-TR-92-543, Stanford, CA, Jul. 1992.
Daniel Hampel & Robert Winder, Threshold Logic, IEEE Spectrum, May 1971, pp. 32-39.
Janusz A. Brzozowski & Carl-Johan H. Seger, Asynchronous Circuits -Monographs in Computer Science, Springer-Verlag New York, Inc., 1995, New York, NY.

Affiliated with

Also associated with

Rating

Null convention adder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Null convention adder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Null convention adder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-396173