NROM structure

Details NROM structure NROM structure

2001-03-22

2004-12-21

Frejd, Russell (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C716S030000

Reexamination Certificate

active

06834263

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90101240, filed Jan. 19, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an NROM structure. More particularly, the present invention relates to a macro model of an NROM structure in simulating the real operation condition of the NROM.
2. Description of Related Art
With the development of the technology, the highly cost and largely occupied vacuum tube is replaced by the bi-polar transistor (BJT) with relatively low cost and high operation speed. However, the disadvantage of the BJT is huge energy consumption. Therefore, heat dissipation of the BJT become a main problem when the integration is increased. In order to solve the problem described above, the MOS is developed.
FIG. 1A
is schematic, cross-sectional view of a conventional N-type MOS. The N-type MOS comprises a substrate
10
, a source
12
, a drain
14
and a gate electrode
16
. Further, a Vsub, a Vs, a Vd and Vg are respectively applied on the substrate
10
, the source
12
, the drain
14
and the gate electrode
16
. The substrate
10
can be a P-type substrate and the drain
14
and the source
12
can be N-type regions, for example. Also, gate electrode
16
is constructed by a metal layer or a polysilicon layer
20
and an underlayer, a gate oxide layer
18
. In order to describe or simulate the operation of the MOS on the computer, the structure of the MOS is represented by circuit symbols.
FIG. 1B
is a circuit symbol of a conventional NMOS transistor.
FIGS. 1C and 1D
are diagrams showing characteristics of the NMOS transistor. Since the source and the substrate of the NMOS are usually grounded, operation of the NMOS is controlled by the Vg and the Vd, wherein the Vg decides the switch state (on/off state) of the NMOS and the Vd decides the amount of the current passing through the drain, channel and source when the NMOS is opened. Therefore, as shown in
FIG. 1C
, the current Id in the NMOS is almost zero when Vg is smaller than Vt. Simultaneously, when Vg is larger than Vt, the current Id in the NMOS is proportionally increased with the Vg. As shown in
FIG. 1D
, under Vg
1
, Vg
2
and Vg
3
(while Vg
1
<Vg
2
<Vg
3
), Id is directly proportional to Vd when Vd is relatively small. When the Vd is increased to reach a saturated drain voltage, the Id is approaching to saturated situation.
Based on the characteristics provided by the curves in
FIGS. 1C and 1D
, various circuit characters of the NMOS shown in
FIG. 1B
can be simulated by the computer.
However, with the development of the different NMOS structure, the NROM structure, such as those shown in U.S. Pat. No. 5,966,603 and U.S. Pat. No. 5,768,192, become more complex than ever and the characters of those NROM with complex structure are quite different from the those of the single NMOS shown in
FIGS. 1C and 1D
. Therefore, the model structure basing on the factors of the single NMOS can not be used to explain the operation phenomenon of the NROM with complex structure. Hence, the NROM with complex structure can not be efficiently simulated by computer.
SUMMARY OF THE INVENTION
The invention provides a macro model of a programmable NROM for simulating the character of the NROM. The NROM comprises a substrate, a drain located in the substrate, a source located in the substrate and a gate electrode located on the substrate between the source and the drain. The gate electrode comprises a first oxide layer, a nitride material layer, a second oxide layer and a polysilicon layer. When the programmable NROM is under a forward reading operation mode, charges are trapped in the nitride material layer close to the drain to form a charge trapped region. The macro model of the NROM comprises a normal MOS symbol element and a short channel MOS symbol element. The normal MOS symbol element represents a first MOS without having the charge trapped region and the first MOS is constructed by a first gate electrode, a first drain and a first source. The short channel MOS symbol element represents a second MOS with the charge trapped region and the second MOS is constructed by a second drain, a second source coupled with the first drain and a second gate electrode coupled with the first gate electrode.
The invention provides a macro model of an NROM for simulating the character of the programmable NROM. The NROM comprises a substrate, a drain located in the substrate, a source located in the substrate and a gate electrode located on the substrate between the source and the drain. The gate electrode comprises a first oxide layer, a nitride material layer, a second oxide layer and a polysilicon layer. When the programmable NROM is under a reverse reading operation mode, charges are trapped in the nitride material layer close to the source to form a charge trapped region. The macro model of the NROM comprises a normal MOS symbol element and a short channel MOS symbol element. The normal MOS symbol element represents a first MOS without having the charge trapped region and the first MOS is constructed by a first gate electrode, a first drain and a first source. The short channel MOS symbol element represents a second MOS with the charge trapped region and the second MOS is constructed by a second source, a second drain coupled with the first source and a second gate electrode coupled with the first gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5768192 (1998-06-01), Eitan
patent: 5966603 (1999-10-01), Eitan
patent: 6580124 (2003-06-01), Cleeves et al.
patent: 6593624 (2003-07-01), Walker
patent: 6677204 (2004-01-01), Cleeves et al.
Tsai et al., W-J. Positive Oxide Charge-Enhanced Read Disturb in a Localized Trapping Storage Flash Memory Cell, IEEE Transactions on Electron Devices, vol. 51, No. 3, Mar. 2004, pp. 434-439.*
Lusky et al., E. Investigation of Channel Hot Electron Injection by Localized Charge-Trapping Nonvolatile Memory Devices, IEEE Transactions on Electron Devices, vol. 51, No. 3, Mar. 2004, pp. 444-451.*
Larcher et al., L. Impact of Programming Charge Distribution on Threshold Voltage and Subthreshold Slope of NROM Memory Cells, IEEE Transactions on Electron Devices, vol. 49, No. 11, Nov. 2002, pp. 1939-1946.*
Chang et al., Y-W. Modeling for the 2nd-Bit Effect of a Nitride-Based Trapping Storage Flash EEPROM Cell Under Two-Bit Operation, IEEE Electron Device Letters, vol. 25, No. 2, Feb. 2004, pp. 95-97.

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