Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2005-11-18
2008-03-18
Tran, Minh-Loan (Department: 2826)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000, C438S287000, C438S589000, C438S591000, C257SE21180, C257SE21423, C257SE21679
Reexamination Certificate
active
07344923
ABSTRACT:
An NROM semiconductor memory device and fabrication method are disclosed. According to one aspect, a method for fabricating an NROM semiconductor memory device can include providing a plurality of u-shaped MOSFETs, which are spaced apart from one another and have a multilayer dielectric. The dielectric suitable for charge trapping along rows in a first direction and alone columns in a second direction in trenches of a semiconductor substrate. Source/drain regions are provided between the u-shaped MOSFETs in interspaces between the rows which run parallel to the columns. Isolation trenches are provided in the source/drain regions between the u-shaped MOSFETs of adjacent columns as far as a particular depth in the semiconductor substrate. The isolation trenches are filled with an insulation material. Word lines are provided for connecting respective rows of u-shaped MOSFETs.
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Hofmann Franz
Landgraf Erhard
Specht Michael
Infineon - Technologies AG
Jenkins Wilson Taylor & Hunt, P.A.
Tran Minh-Loan
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