Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device
Reexamination Certificate
2002-06-14
2004-08-17
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Charge transfer device
C257S202000, C257S215000, C257S216000, C257S288000, C438S257000
Reexamination Certificate
active
06777725
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated memory circuit, and in particular, to so-called NROM memories that are based on a dielectric layer for storing information.
BACKGROUND OF THE INVENTION AND PRIOR ART
In the technical publication “Can NROM, two-bit, trapping storage NVM cell, give a real challenge to floating gate cells?”, B. Eitan et al., International Conference on Solid State Devices and Materials, Tokyo, 1999, discloses a memory circuit having an array of NROM memory cells. The NROM concept is a two bit Flash cell based on charge storage in an ONO dielectric. ONO stands for oxide-nitride-oxide. One memory cell is storing two physically separated bits with a unique method to sense the trapped charge. Programming is performed by Channel Hot Electron injection (CHE) and erase is performed by tunnelling enhanced Hot Hole Injection.
Gene rally, a NROM cell is a n-channel MOSFET device where the gate dielectric is replaced by a trapping material (nitride) sandwiched between two silicon dioxide layers. This is the above mentioned ONO structure. The top and bottom oxides are thicker than 1,5 nanometers to avoid any direct tunneling. The charge is stored in nitride next to the n
+
junctions. Each NROM cell includes a source region, a drain region and a channel region extending between the source and the drain region.
In this prior art memory cell, the drain regions on the one hand and the source regions on the other hand of neighboring memory cells are connected by so-called bit lines that are highly doped regions within the substrate semiconductor material. Generally, a p doped semiconductor substrate is used. The bit lines are realized as heavily doped n regions. Above the heavily doped n regions, an oxide for insulation purposes—the bit line oxide—is provided. This kind of bit lines are called “buried” bit lines.
Above the channel region, the ONO structure is applied. Above the ONO structure, the “gate electrode” that is also called word line is provided. In particular, word lines are provided such that they cross the bit lines at angles of approximately 90°. Such an area of memory cells being comprised of an array of parallel bit lines and an array of parallel word lines being formed above the bit lines and crossing the bit lines at 90° angles is called a virtual ground array. Usually, this virtual ground array is a field-oxide-less cross point architecture with a 5-6 F
2
cell size or 2.5-3 F
2
per bit.
The NROM cell is programmed by channel hot electron injection. At a high gate potential the transistor is driven into pinch off, if a sufficient source to drain voltage is applied. Electrons are heating up at high fields near the drain junction. As soon as the electrons have reached a certain velocity, they are injected into the nitride layer of the ONO structure because of the corresponding voltage applied to the word line, i.e., the gate of the NROM memory cell.
This electron injection into the nitride layer takes place near the metallurgical junction of the drain region to which the electrons move. Since the electrons can not freely move within the nitride layer, the electrons are trapped approximately at the edge of a crossing region of a word line and a bit line.
When the drain source voltage is reversed, electrons are accelerated in the reverse direction. When these electrons have reached a certain velocity, they are injected into the nitride layer near the crossing region of the word line and the other bit line of the memory cell. Since the electrons are not freely movable within the nitride layer of the ONO structure, one memory cell can store two bits. The storing locations are the edges of the crossing point of the word line and the first bit line of a memory cell, and the edges of the other crossing point of the word line and the other bit line of the memory cell.
Generally, it is a design aim to minimize the size of a memory cell. When the cell size can be reduced, the memory circuit having a certain storage capacity can be made smaller. The other way round, a memory circuit having the same size has a higher storage capacity, when a memory cell is made smaller.
A former limitation to memory cell minimization was the fact that a certain channel length is required for the device. The barrier heights of the layer materials are around 3.1 eV which requires the electrons to be heated up enough to surpass this barrier during programming. A typical drain voltage is, therefore, 5 V. To avoid punch through the effective channel length can not be reduced as much as desired.
To minimize the cell size while maintaining a certain required channel length, the U.S. patent application publication U.S. Ser. No. 2002/0024092 A1 teaches to use a grooved channel region. The channel shape is changed from a straight channel shape to a kind of a two dimensional channel shape, since the active channel is not formed by a straight connection but by U shape or V shape at the bottom of a channel groove. The ONO structure is applied onto the surface of the channel groove. With this groove shape, the memory cell size can be reduced in order to accommodate a higher capacity memory on a certain chip size.
The memory cell in the above identified US patent application publication has diffused bit lines, i.e., bit lines, that are produced by heavily doping certain regions of the semiconductor substrate.
It is well known that instead of heavily doping, these bit lines still have a certain ohmic resistance that is much higher than the ohmic resistance of a metallic layer for example. On the other side, relatively high voltages have to be applied to the drain or source region. The voltages lie in the range of 4.5 volts. To reduce ohmic losses in the bit lines, the so-called bit line strapping technique is used. With this technique, via holes are applied between adjacent word lines. These via holes extend between a top metal or metallized layer and the bit line, i.e., the diffused regions that are heavily doped. With this arrangement, the ohmic resistance of the bit lines is not mainly determined by the heavily doped diffused regions but is determined by the ohmic resistances of the metal or metallized layer and the contact via holes.
A disadvantage of this concept is that it becomes increasingly difficult to produce these via holes between adjacent word lines, since the patterning of the word lines is to be conducted by photolithography. Additionally, the word line photolithography is a very demanding task, since the structures are in the range of 150 to 50 nanometers. One can imagine that it is very difficult to apply a via hole which itself has a diameter of possibly 50 nanometers in a space of only 100 nanometers or less. Due to the relatively high maximum voltage (about 10 V) between bit lines and word lines a sufficient insulation layer thickness is required if reliability problems are to be avoided. In addition, the word line to bit line capacity should be kept low to avoid switching delay.
To address this problem, we have proposed in our commonly assigned, copending application Ser. No. 09/600,649, filed Jul. 6, 2001, to not use the bit line strapping technique but to apply a bit line structure having several layers onto the semiconductor substrate. Bit lines are formed of a polysilicon layer directly applied to the substrate semiconductor surface. On this polysilicon layer a metal containing layer is applied. This metal containing layer is, e.g. tungsten silicide and, additionally, a hard mask layer, e.g. an oxide, for electric insulation of the tungsten silicide layer from the respective environment. Thus, this bit line applied on top of the substrate is formed of a polysilicon layer, a tungsten silicide layer and a top oxide layer. Instead of WSi, also tungsten nitride and tungsten can be applied. Additionally, titan and/or titan silicide can be used.
It has been discovered that, though the problems involved with bit line strapping are overcome by this solution, another problem has appeared. It has been outlined above, that the word line lithograph
Palm Herbert
Willer Josef
Flynn Nathan J.
Ingentix GmbH & Co. KG
Wilson Scott R
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