NPN transistor with P/N closed loop in contact with collector el

Details NPN transistor with P/N closed loop in contact with collector el NPN transistor with P/N closed loop in contact with collector el

1985-07-09

1987-03-24

Carroll, J.

357 20, 357 48, 357 86, H01L 2906, H01L 2704, H01L 2972

Patent

active

046529004

ABSTRACT:
A semiconductor device capable of suppressing the influence of a parasitic pnp transistor caused when an npn transistor operates in saturation range in such a way that a p-type impurity region is formed in the outer layer of an n-type collector region and electrically short-circuited with the n-type collector region isolated by a p-type isolation diffusion layer in the npn bi-polar transistor.

REFERENCES:
patent: 3590345 (1971-06-01), Brewer et al.
patent: 3676714 (1972-07-01), Wensink et al.
patent: 3878551 (1975-04-01), Callahan, Jr.
patent: 4027325 (1977-05-01), Genesi
patent: 4117507 (1978-09-01), Pacor
patent: 4236164 (1980-11-01), Tang et al.
patent: 4276556 (1981-06-01), Enomoto et al.
patent: 4303932 (1981-12-01), Johannsen
Berger et al., "Speed Enhancement of Saturated Transistors" IBM Tech. Disc. Bull., vol. 20, No. 2, pp. 636-637, Jul. 1977.

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