Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2000-04-11
2004-07-20
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S198000, C257S200000, C257S201000
Reexamination Certificate
active
06765242
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to transistor structures and to methods for their fabrication, and in particular to an NPN double heterostructure bipolar transistor (DHBT) fabricated on a gallium arsenide (GaAs) substrate and having an indium gallium arsenide nitride (InGaAsN) base region.
BACKGROUND OF THE INVENTION
The growing market of portable electronic devices including cellular telephones demands high-performance electronic circuitry having minimal power dissipation to prolong battery life. Reducing the power dissipation of electronic circuitry requires transistors that operate with a small voltage swing. One approach that has been used to form heterostructure bipolar transistors (HBTs) having a low voltage swing has been to form a GaAs transistor having a strained indium gallium arsenide (InGaAs) base region, with the substrate being GaAs. A disadvantage of this approach is that the amount of indium that can be incorporated into the base region to lower the voltage swing is limited due to the formation of misfit dislocations as the InGaAs base becomes increasingly strained relative to the GaAs substrate.
Another approach that has been used is to form the HBT with a lattice-matched InGaAs base on an indium phosphide (InP) substrate so that more indium can be incorporated into the base region without the formation of misfit dislocations. This is the approach that is currently used for fabricating low-power HBTs. However, the unavailability of large-size (>4 inches in diameter) InP substrates and the relatively high cost of InP substrates compared to GaAs substrates makes production costs relatively high when using this approach so that its use has not become widespread in the consumer marketplace.
The present invention relates to an NPN double-heterostructure bipolar transistor (DHBT) which is based on the use of a p-doped indium gallium arsenide nitride (InGaAsN) layer for the base region. The collector region of the transistor can be formed of GaAs or InGaAsN; and the emitter region can be formed of indium gallium phosphide (InGaP), GaAs or aluminum gallium arsenide (AlGaAs).
An advantage of the present invention is that the transistor can be fabricated on GaAs substrates which are available in large sizes (4 to 6 inches in diameter) and at lower cost than alternative substrates (e.g. InP), thereby potentially reducing fabrication costs, and also allowing fabrication in commercial GaAs foundries.
Another advantage of the present invention is that the use of InGaAsN for the p-type base region of the NPN transistor can provide a reduced voltage swing, thereby reducing power dissipation in the transistor.
A further advantage of the present invention is that the structure of the transistor can be made substantially strain-free with the InGaAsN base region substantially lattice-matched to the GaAs substrate.
Yet another advantage of the present invention is that the transistor can operate up to very high frequencies on the order of 50 GHz or more.
These and other advantages of the method of the present invention will become evident to those skilled in the art.
SUMMARY OF THE INVENTION
The present invention relates to an NPN double-heterojunction bipolar transistor (DHBT) formed on a gallium arsenide (GaAs) substrate (e.g. a semi-insulating GaAs substrate). The transistor comprises a base region which further comprises a layer of p-type-doped indium gallium arsenide nitride (InGaAsN). An emitter region is located on one side of the base region and further comprises a layer of a first n-type-doped semiconductor having a bandgap energy greater than the bandgap energy of the InGaAsN base region. A collector region is located on the other side of the InGaAsN base region and further comprises a layer of a second n-type-doped semiconductor having a bandgap energy greater than or equal to the bandgap energy of the InGaAsN base region. Electrodes are provided on the NPN transistor to form separate electrical connections to each of the collector, emitter and base regions. The first n-type-doped semiconductor forming the emitter region can comprise GaAs, aluminum gallium arsenide (AlGaAs), or indium gallium phosphide (InGaP); and the second n-type-doped semiconductor forming the collector region can comprise GaAs or InGaAsN.
The InGaAsN base region comprises the semiconductor alloy composition In
x
Ga
1−x
As
1−y
N
y
with 0<x≦0.1 and with 0<y≦0.03. Alternately, the base region can comprise a compositionally-graded In
x
Ga
1−x
As
1−y
N
y
layer having y<0.01 near the emitter region and a larger value of 0.01≦y≦0.03 near the collector region. The p-type doping of the InGaAsN base region can also be varied in concentration across the base region with a higher level of the p-type-doping (e.g. 10
19
cm
−3
) being provided near the emitter region and with a lower level of the p-type doping (e.g. 10
17
cm
−3
) being provided near the collector region.
The NPN double-heterojunction bipolar transistor can further include a first bandgap-smoothing transition region (also termed herein a first transition region or a first transition layer) located between the base and collector regions. The first bandgap-smoothing transition region can comprise a layer of compositionally-graded indium gallium arsenide (InGaAs) or InGaAsN with n-type doping. In the case of an InGaAs first transition region, the semiconductor alloy composition of the InGaas can comprise In
x
Ga
1−x
As with x varying across the transition region from a low value of x (e.g. x<0.1) near the collector region to a higher value of x (e.g. 0.1≦x≦0.4) near the base region. In the case of an InGaAsN first transition region, the semiconductor alloy composition of the InGaAsN can comprise In
x
Ga
1−x
As
1−y
N
y
with x and y varying (i.e. stepped or graded in composition) from low values of x and y (e.g. x=0 and y=0) near the collector region to higher values of x and y (e.g. x≧0.03 and y≧0.01) near the base region. By appropriate epitaxial growth of the In
x
Ga
1−x
As
1−y
N
y
transition region (i.e. with x=3y), the first transition region can be formed substantially strain-free. The first transition region can further comprise a delta-doped portion (i.e. a sheet of n-type doping of, for example, 5×10
12
cm
−2
).
In some embodiments of the present invention, a second bandgap-smoothing transition region can be provided in the transistor between the base and emitter regions. This second bandgap-smoothing transition region with n-type doping can further include a delta-doped portion (e.g. a sheet of n-type doping of, for example, 5×10
12
cm
−2
). When the emitter region comprises InGaP or AlGaAs, the second bandgap-smoothing transition region can comprise, for example, Al
x
Ga
1−x
As with x varying across the second bandgap-smoothing transition region from x=0 near the base region to a value of x that provides a bandgap energy substantially equal to that of the InGaP or AlGaAs emitter region.
A passivation layer can be provided on the transistor overlying exposed portions of the collector, emitter and base regions of the transistor to improve performance by reducing effects due to surface recombination. The passivation layer can comprise, for example, a layer of silicon oxynitride.
The present invention also relates to an NPN double-heterojunction bipolar transistor formed on a GaAs substrate and comprising a plurality of semiconductor layers epitaxially grown on the substrate, including a layer of GaAs with n-type doping forming a collector region of the transistor, a layer of indium gallium phosphide (InGaP) with n-type doping forming an emitter region of the transistor, and a layer of indium gallium arsenide nitride (InGaAsN) with p-type doping forming a base region which is sandwiched between the collector and emitter regions. Electrodes are provided on the transistor to separately contact each of the collector, emitter and base regions.
The c
Ashby Carol I. H.
Baca Albert G.
Chang Ping-Chih
Hou Hong Q.
Li Nein-Yi
Hohimer John P.
Sandia Corporation
LandOfFree
Npn double heterostructure bipolar transistor with ingaasn... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Npn double heterostructure bipolar transistor with ingaasn..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Npn double heterostructure bipolar transistor with ingaasn... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3201670