NPM Anti-saturation clamp for NPN logic gate transistor

Details NPM Anti-saturation clamp for NPN logic gate transistor NPM Anti-saturation clamp for NPN logic gate transistor

1981-04-13

1983-09-20

Edlow, Martin H.

357 92, 357 86, 357 46, H01L 2948

Patent

active

044059345

ABSTRACT:
A bipolar logic gate formed in an isolated N-type epitaxial layer in an integrated circuit device includes a normally operated vertical NPN switch transistor clamped by an inversely operated NPM clamp transistor. The base of the clamp transistor is formed by a high energy boron ion implant into a portion of the N-type epitaxial layer extending through the P-type base of the switch transistor. Multiple outputs are provided by Schottky barrier diodes formed on the N-type epitaxial layer.

REFERENCES:
patent: 3909837 (1975-09-01), Kronlage
patent: 3943552 (1976-03-01), Shannon et al.
Sloan, IEEE Int. Electron Devices Meeting, Technical Digest, Dec. 2, 1979, "STL Technology", pp. 324-327.
Lohstroh, J., IEEE Journal of Solid-State Circuits, vol. SC-14, No. 3, Jun. 1979, "ISL, A Fast and Dense Low-Power Logic, Made in a Standard Schottky Process", pp. 585-590.

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