Normally off InP field effect transistor making process

Details Normally off InP field effect transistor making process Normally off InP field effect transistor making process

1981-03-30

1983-02-08

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 29591, 148178, H01L 2124

Patent

active

043720323

ABSTRACT:
A normally off insulated gate field effect transistor having a p-type sin crystal InP substrate with source and drain contacts spaced apart and disposed thereon with a layer of silicon dioxide disposed over the InP material in the space between the contacts and a gate electrode disposed on the silicon dioxide to completely bridge the space between the contacts. The p-type single crystal InP substrate may be replaced by a p-type epitaxial InP material disposed on a semi-insulating InP substrate.

REFERENCES:
patent: 3012175 (1961-12-01), Jones et al.
patent: 3460005 (1969-08-01), Kanda et al.
patent: 3821777 (1974-06-01), James
patent: 4161739 (1979-07-01), Messick
patent: 4252580 (1981-02-01), Messick
Balk et al., IBM Tech. Discl. Bull., vol. 10, No. 8, Jan. 1968, p. 1277.

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