Normally-off, gate-controlled electrical circuit with low on-res

Details Normally-off, gate-controlled electrical circuit with low on-res Normally-off, gate-controlled electrical circuit with low on-res

1983-03-07

1985-06-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307581, 307252A, 307252Q, 307304, H03K 1760, H03K 3353

Patent

active

045231117

ABSTRACT:
An electrical circuit includes a JFET serially connected to an IGFET, the gate of the IGFET constituting the gate for the circuit. Biasing structure, such as a resistor, is connected between the circuit gate and the gate of the JFET for forward-biasing the P-N junction of the JFET extant between its gate and channel regions. When this P-N junction is biased by more than about 0.6 volts for a silicon JFET, the JFET gate region injects current carriers into the JFET channel region, whereby bipolar conduction occurs in the JFET channel region and low on-resistance for the circuit is achieved. In a preferred circuit the biasing structure comprises an IGFET, which advantageously results in the circuit gate having a high input impedance.

REFERENCES:
patent: 3521141 (1970-07-01), Walton
B. J. Baliga, "Bipolar Operation of Power Junction Field-Effect Transistors", Electronics Letters, vol. 16 (Apr. 1980), pp. 300-301.

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