Normalizing pipelined floating point processing unit

Details Normalizing pipelined floating point processing unit Normalizing pipelined floating point processing unit

1991-07-23

1993-11-30

Nguyen, Long T.

Boots, shoes, and leggings

36471504, G06F 738

Patent

active

052671860

ABSTRACT:
A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent. If the result has a zero or negative exponent, the result is directed through the second arithmetic unit a second time so that the result is denormalized. The denormalized result is then output.

REFERENCES:
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patent: 4896286 (1990-01-01), Ueda
patent: 4901267 (1990-02-01), Birman et al.
patent: 5040138 (1991-08-01), Maher, III
patent: 5058408 (1991-10-01), Gupta et al.

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