Normalization shift prediction independent of operand subtractio

Details Normalization shift prediction independent of operand subtractio Normalization shift prediction independent of operand subtractio

1998-11-13

2000-08-08

Malzahn, David H.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 501

Patent

active

061015164

ABSTRACT:
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

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