Normalization processing apparatus

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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08046395

ABSTRACT:
A normalization processing apparatus according to an embodiment of the present invention can calculate all of normalization processing output values, that is, the output value of the size of a region, the output value of the lowest value in the region, the output value of the number of non-output bits, and an output bit string, at the same time using a shift amount and the prefix and suffix of the output bit string. The shift amount is calculated using an input value of the size of the region. The prefix and the suffix are calculated using an input value of the lowest value in the region and an input value of the number of non-output bits.

REFERENCES:
patent: 6765515 (2004-07-01), Miyamoto
patent: 7495588 (2009-02-01), Otsuka
patent: 7528749 (2009-05-01), Otsuka
patent: 2003/0217085 (2003-11-01), Miyamoto
patent: 2005/0156762 (2005-07-01), Tsuru
patent: 2005/0270192 (2005-12-01), Tsuru
patent: 2008/0100479 (2008-05-01), Otsuka
patent: 2008/0100480 (2008-05-01), Otsuka
patent: 2008/0104154 (2008-05-01), Suzuki
Mo Li, Wuchen Wu, A High Throughput Binary Arithmetic Coding Engine for h.264/AVC, 2006.

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